Enhanced PCIe auto-bifurcation

Abstract

An information handling system may include at least one processor; a slot configured to receive an information handling resource and couple the information handling resource to a communications bus of the information handling system; and a computer-readable medium having instructions thereon that are executable by the at least one processor. The instructions may be executable for determining logical states for a plurality of pins of the slot; based on the determined logical states, determining a communications width associated with an information handling resource received in the slot; and setting a bifurcation variable associated with the slot based on the determined communications width.

What is claimed is: 
     
       1. An information handling system comprising:
 at least one processor; 
 a slot configured to receive an information handling resource and couple the information handling resource to a communications bus of the information handling system, wherein the communications bus is a Peripheral Component Interconnect Express (PCIe) bus; and 
 a computer-readable medium having instructions thereon that are executable by the at least one processor for: 
 determining logical states for a plurality of PRSNT2# pins of the slot, wherein the plurality of PRSNT2# pins of the slot are associated with a PRSNT2# signal, and wherein at least one of the plurality of PRSNT2# pins is electrically coupled to a pin associated with a PRSNT1# signal via a conductive trace on the information handling resource; 
 based on which of the PRSNT2# pins have a logical zero state associated therewith, determining a communications width associated with an information handling resource received in the slot; and 
 setting a bifurcation variable associated with the slot based on the determined communications width. 
 
     
     
       2. The information handling system of  claim 1 , wherein the instructions are further executable for restarting the information handling system after the setting. 
     
     
       3. The information handling system of  claim 1 , wherein the computer-readable medium includes a Basic Input/Output System (BIOS). 
     
     
       4. The information handling system of  claim 1 , wherein the determining the logical states comprises determining voltages. 
     
     
       5. The information handling system of  claim 1 , wherein the logical states are determined via a plurality of general purpose input/output (GPIO) pins of a platform controller hub of the information handling system. 
     
     
       6. The information handling system of  claim 1 , wherein a logical zero state associated with a B17 pin corresponds to a PCIe ×1 information handling resource. 
     
     
       7. The information handling system of  claim 6 , wherein a logical zero state associated with a B31 pin corresponds to a PCIe ×4 information handling resource. 
     
     
       8. The information handling system of  claim 7 , wherein a logical zero state associated with a B48 pin corresponds to a PCIe ×8 information handling resource. 
     
     
       9. The information handling system of  claim 8 , wherein a logical zero state associated with a B81 pin corresponds to a PCIe ×16 information handling resource. 
     
     
       10. The information handling system of  claim 1 , wherein the information handling resource does not implement PCIe lane reversal, and wherein the setting of the bifurcation variable is configured to prevent a failure of an automatic bifurcation with respect to the information handling resource. 
     
     
       11. A method comprising:
 an information handling system receiving an information handling resource in a slot that is configured to couple the information handling resource to a communications bus of the information handling system, wherein the communications bus is a Peripheral Component Interconnect Express (PCIe) bus; 
 the information handling system determining logical states for a plurality of PRSNT2# pins of the slot, wherein the plurality of PRSNT2# pins of the slot are associated with a PRSNT2# signal, and wherein at least one of the plurality of PRSNT2# pins is electrically coupled to a pin associated with a PRSNT1# signal via a conductive trace on the information handling resource; 
 based on which of the PRSNT2# pins have a logical zero state associated therewith, the information handling system determining a communications width associated with an information handling resource received in the slot; and 
 the information handling system setting a bifurcation variable associated with the slot based on the determined communications width. 
 
     
     
       12. The method of  claim 11 , wherein:
 a logical zero state associated with a B17 pin corresponds to a PCIe ×1 information handling resource, a logical zero state associated with a B31 pin corresponds to a PCIe ×4 information handling resource, a logical zero state associated with a B48 pin corresponds to a PCIe ×8 information handling resource, and a logical zero state associated with a B81 pin corresponds to a PCIe ×16 information handling resource. 
 
     
     
       13. The method of  claim 11 , wherein the information handling resource does not implement PCIe lane reversal, and wherein the setting of the bifurcation variable is configured to prevent a failure of an automatic bifurcation with respect to the information handling resource. 
     
     
       14. An article of manufacture comprising a non-transitory, computer-readable medium having computer-executable code thereon that is executable by a processor for:
 in response to a slot coupled to the processor receiving an information handling resource in a slot that is configured to couple the information handling resource to a communications bus, determining logical states for a plurality of PRSNT2# pins of the slot, wherein the communications bus is a Peripheral Component Interconnect Express (PCIe) bus, wherein the plurality of PRSNT2# pins of the slot are associated with a PRSNT2# signal, and wherein at least one of the plurality of PRSNT2# pins is electrically coupled to a pin associated with a PRSNT1# signal via a conductive trace on the information handling resource; 
 based on which of the PRSNT2# pins have a logical zero state associated therewith, determining a communications width associated with an information handling resource received in the slot; and 
 setting a bifurcation variable associated with the slot based on the determined communications width. 
 
     
     
       15. The article of  claim 14 , wherein a logical zero state associated with a B17 pin corresponds to a PCIe ×1 information handling resource. 
     
     
       16. The article of  claim 14 , wherein a logical zero state associated with a B31 pin corresponds to a PCIe ×4 information handling resource. 
     
     
       17. The article of  claim 14 , wherein a logical zero state associated with a B48 pin corresponds to a PCIe ×8 information handling resource. 
     
     
       18. The article of  claim 14 , wherein a logical zero state associated with a B81 pin corresponds to a PCIe ×16 information handling resource. 
     
     
       19. The article of  claim 14 , wherein the information handling resource does not implement PCIe lane reversal, and wherein the setting of the bifurcation variable is configured to prevent a failure of an automatic bifurcation with respect to the information handling resource.