Antifuse OTP structure with hybrid junctions

Abstract

An antifuse One-Time-Programmable memory cell includes a substrate, a select transistor, and an antifuse capacitor. The select transistor includes a first high-voltage junction formed in the substrate and a first low-voltage junction formed in the substrate. The antifuse capacitor includes a second high-voltage junction formed in the substrate and a second low-voltage junction formed in the substrate.

What is claimed is: 
     
       1. An antifuse One-Time-Programmable memory cell, comprising:
 a substrate; 
 a select transistor formed on the substrate, wherein the select transistor includes:
 a first gate dielectric layer formed on the substrate, 
 a first gate formed on the gate dielectric layer; 
 a first high-voltage junction formed in the substrate; and 
 a first low-voltage junction formed in the substrate, 
 
 wherein a source and a drain for the select transistor are respectively formed by the first high-voltage junction and the first low-voltage junction, or respectively formed by the first low-voltage junction and the first high-voltage junction, 
 wherein the first high-voltage junction has a first breakdown threshold voltage higher than the first low-voltage junction; and 
 an antifuse capacitor formed on the substrate, wherein the antifuse capacitor includes:
 a second gate dielectric layer formed on the substrate, 
 a second gate formed on the gate dielectric layer; 
 a second high-voltage junction formed in the substrate; and 
 a second low-voltage junction formed in the substrate, 
 
 wherein a source and a drain for the antifuse capacitor are respectively formed by the second high-voltage junction and the second low-voltage junction, or respectively formed by the second low-voltage junction and the second high-voltage junction, 
 wherein the second high-voltage junction has a second breakdown threshold voltage higher than the second low-voltage junction. 
 
     
     
       2. The antifuse One-Time-Programmable memory cell of  claim 1 , wherein the first high-voltage junction or the second high-voltage junction has a threshold junction breakdown voltage above 3.3 Volt. 
     
     
       3. The antifuse One-Time-Programmable memory cell of  claim 2 , wherein the first high-voltage junction or the second high-voltage junction has a threshold junction breakdown voltage above 5 Volt. 
     
     
       4. The antifuse One-Time-Programmable memory cell of  claim 1 , wherein the first low-voltage junction or the second low-voltage junction has a threshold junction breakdown voltage below 3.2 Volt. 
     
     
       5. The antifuse One-Time-Programmable memory cell of  claim 4 , wherein the first low-voltage junction or the second low-voltage junction has a threshold junction breakdown voltage below 2.3 Volt. 
     
     
       6. The antifuse One-Time-Programmable memory cell of  claim 1 , wherein the first high-voltage junction and the second high-voltage junction are electrically connected. 
     
     
       7. The antifuse One-Time-Programmable memory cell of  claim 1 , wherein at least one of the first high-voltage junction or the second high-voltage junction includes two doped regions having different doping levels. 
     
     
       8. The antifuse One-Time-Programmable memory cell of  claim 7 , wherein the first high-voltage junction includes a first doped region adjacent to the first gate dielectric layer at a lower doped level than a second doped region away from the first gate dielectric layer. 
     
     
       9. The antifuse One-Time-Programmable memory cell of  claim 7 , wherein the second high-voltage junction includes a first doped region adjacent to the second gate dielectric layer at a lower doped level than a second doped region away from the second gate dielectric layer. 
     
     
       10. The antifuse One-Time-Programmable memory cell of  claim 7 , wherein one of the two doped regions has an electrically active concentration of dopant level in a range of 3×10 17 ˜1×10 19  atoms/cm −3 , wherein another one of the two doped regions has an electrically active concentration of dopant level above 2×10 19  atoms/cm −3 . 
     
     
       11. The antifuse One-Time-Programmable memory cell of  claim 1 , wherein at least one of the first low-voltage junction or the second low-voltage junction includes two doped regions having different doping levels. 
     
     
       12. The antifuse One-Time-Programmable memory cell of  claim 11 , wherein the first low-voltage junction includes a first doped region adjacent to the first gate dielectric layer at a lower doped level than a second doped region away from the first gate dielectric layer. 
     
     
       13. The antifuse One-Time-Programmable memory cell of  claim 11 , wherein the second low-voltage junction includes a first doped region adjacent to the second gate dielectric layer at a lower doped level than a second doped region away from the second gate dielectric layer. 
     
     
       14. The antifuse One-Time-Programmable memory cell of  claim 1 , wherein the first high-voltage junction has a more gradual junction doping profiles than the first low-voltage junction, wherein the second high-voltage junction has a more gradual junction doping profiles than the second first low-voltage junction. 
     
     
       15. The antifuse One-Time-Programmable memory cell of  claim 1 , wherein the first high-voltage junction has a doping profiles annealed for a longer period than the first low-voltage junction, wherein the second high-voltage junction has a doping profiles annealed for a longer period than the second low-voltage junction.