Protecting chips from electromagnetic pulse attacks using an antenna

Abstract

An on-chip electromagnetic (EM) pulse protection circuit detects EM pulse attacks, generates an alarm, and performs a defensive action to protect the integrated circuit. The EM pulse protection circuit can be used with various integrated circuits or manufactured chips in which, for example, there is a desire to keep information secure, maintain the security of the chip, secure boot processes, and/or protect private keys.

What is claimed is: 
     
       1. An electromagnetic (EM) pulse protection circuit for an integrated circuit, comprising:
 alarm circuitry configured to receive a detection signal and, in response thereof, generate an alarm signal that indicates detection of an EM pulse attack; 
 detection circuitry including an antenna configured to generate the detection signal in response to the EM pulse attack on the integrated circuit, wherein the detection signal is a differential voltage induced at two terminals of the antenna, and wherein the EM pulse protection circuit is located on-chip with the integrated circuit; and 
 validation circuitry configured to validate integrity of the antenna by checking latency of a signal propagating through the antenna, wherein the latency of the signal propagating through the antenna is determined by sending a signal from one terminal of the antenna to another terminal of the antenna and comparing a time the signal propagates from the one terminal of the antenna to the other terminal of the antenna with a known standard. 
 
     
     
       2. The EM pulse protection circuit as recited in  claim 1  further comprising an amplifier configured to receive and amplify the detection signal, and provide the amplified detection signal to the alarm circuitry to generate the alarm signal. 
     
     
       3. The EM pulse protection circuit as recited in  claim 1  wherein the differential voltage induced is due to mutual coupling (k) between the antenna and an attack probe coil used for the EM pulse attack. 
     
     
       4. The EM pulse protection circuit as recited in  claim 1  wherein the antenna is an on-chip, center-tapped antenna. 
     
     
       5. The EM pulse protection circuit as recited in  claim 1  wherein the antenna is a planar antenna integrated on the integrated circuit. 
     
     
       6. The EM pulse protection circuit as recited in  claim 1  wherein the detection signal is an analog signal and the alarm circuitry converts the detection signal to a digital alarm signal. 
     
     
       7. The EM pulse protection circuit as recited in  claim 6  wherein the alarm circuitry includes a comparator that receives and processes the detection signal, and provides an output to a logic gate to generate the digital alarm signal. 
     
     
       8. The EM pulse protection circuit as recited in  claim 7  wherein the comparator is a Schmitt trigger that produces a clock edge for the logic gate to generate the digital alarm signal. 
     
     
       9. The EM pulse protection circuit as recited in  claim 8  further comprising an op amp configured to receive and amplify the detection signal, and provide the amplified detection signal to the Schmitt trigger. 
     
     
       10. The EM pulse protection circuit as recited in  claim 1  wherein the EM pulse protection circuit is an on-chip circuit that is integrated in a silicon level of the integrated circuit. 
     
     
       11. The EM pulse protection circuit as recited in  claim 1  wherein the EM pulse protection circuit is an on-chip circuit that is positioned on an electronic package including the integrated circuit. 
     
     
       12. The EM pulse protection circuit as recited in  claim 1  further comprising a response circuit configured to receive the alarm signal and perform a defensive action in response. 
     
     
       13. The EM pulse protection circuit as recited in  claim 12  wherein the defensive action is one or more items selected from the list consisting of:
 disable the integrated circuit, 
 reset the integrated circuit, 
 alter data stored on the integrated circuit, 
 hide data that is on the integrated circuit, 
 track the EM pulse attack, and 
 provide incorrect data. 
 
     
     
       14. An integrated circuit, comprising:
 circuitry configured to perform a function; and 
 an electromagnetic (EM) pulse protection circuit having validation circuitry and detection circuitry with an antenna that generates a detection signal in response to an EM pulse attack on the integrated circuit, wherein the detection signal is a differential voltage induced at two terminals of the antenna, wherein the EM pulse protection circuit is located on-chip with the integrated circuit, wherein the validation circuitry is configured to validate integrity of the antenna by checking latency of a signal propagating through the antenna, and wherein the latency of the signal propagating through the antenna is determined by sending a signal from one terminal of the antenna to another terminal of the antenna and comparing a time the signal propagates from the one terminal of the antenna to the other terminal of the antenna with a known standard. 
 
     
     
       15. The integrated circuit as recited in  claim 14  wherein the differential voltage is due to mutual coupling (k) between the antenna and an attack probe coil used for the EM pulse attack. 
     
     
       16. The integrated circuit as recited in  claim 14  wherein the antenna is an on-chip, center-tapped antenna. 
     
     
       17. The integrated circuit as recited in  claim 14  wherein the antenna is a planar antenna integrated on the integrated circuit. 
     
     
       18. The integrated circuit as recited in  claim 14  wherein the EM pulse protection circuit further includes alarm circuitry that receives the detection signal and generates an alarm signal that indicates detection of the EM pulse attack. 
     
     
       19. The integrated circuit as recited in  claim 18  further comprising a response circuit configured to receive the alarm signal and perform a defensive action in response. 
     
     
       20. The integrated circuit as recited in  claim 19  further comprising multiple EM pulse protection circuits distributed across the integrated circuit. 
     
     
       21. A method of protecting an integrated circuit from an electromagnetic (EM) pulse attack, comprising:
 detecting, via an on-chip circuit, an induced voltage at two terminals of an on-chip antenna in response to an EM pulse attack voltage on the integrated circuit; 
 generating an alarm signal when the induced voltage exceeds a voltage threshold; 
 performing a defensive action is response to the alarm signal; and 
 validating integrity of the antenna by checking latency of a signal propagating through the antenna, wherein the latency of the signal propagating through the antenna is determined by sending a signal from one terminal of the antenna to another terminal of the antenna and comparing a time the signal propagates from the one terminal of the antenna to the other terminal of the antenna with a known standard. 
 
     
     
       22. The method as recited in  claim 21  wherein the on-chip antenna is integrated in a silicon level of the integrated circuit. 
     
     
       23. The method as recited in  claim 21  wherein a value of the voltage threshold is selected for the EM pulse attack voltage.