Active matrix substrate and liquid crystal display apparatus

Abstract

An active matrix substrate includes a gate metal layer, a source metal layer, an interlayer insulating layer, a first transparent conductive layer and second transparent conductive layer formed on or above the interlayer insulating layer, and a lower metal layer formed below the gate metal layer. The lower metal layer includes a plurality of CS bus lines each extending in a column direction and not overlapping a plurality of source bus lines. Each of the plurality of pixels has a drain extension section extending from a drain electrode, a first transparent electrode, a second transparent electrode connected to the drain extension section, and an auxiliary capacitor electrode that includes the lower metal layer and/or the gate metal layer, is electrically connected to at least any one of the plurality of CS bus lines, and overlaps the drain extension section when viewed in a normal direction of the substrate.

The invention claimed is: 
     
       1. An active matrix substrate that has a plurality of pixels arranged in a matrix having a plurality of rows and a plurality of columns, the active matrix substrate comprising:
 a plurality of first TFTs each associated with any one of the plurality of pixels; 
 a plurality of gate bus lines each extending in a row direction; and 
 a plurality of source bus lines each extending in a column direction, 
 wherein the plurality of gate bus lines include a first gate bus line and a second gate bus line associated with each of the plurality of pixel rows, 
 wherein in each of the plurality of pixel rows, when a pixel associated with the first gate bus line is set as a first pixel, and the pixel associated with the second gate bus line is set as a second pixel, 
 each of the plurality of source bus lines is associated with at least two pixel columns including the first pixel and the second pixel included in each of the plurality of pixel rows, 
 wherein the active matrix substrate further comprises:
 a substrate; 
 a gate metal layer that is supported by the substrate and includes, out of a first gate electrode, a first source electrode, and a first drain electrode included in the plurality of first TFTs, the first gate electrode, and the plurality of gate bus lines; 
 a gate insulating layer formed on the gate metal layer; 
 a source metal layer that is formed on the gate insulating layer and includes the first source electrode, the first drain electrode, and the plurality of source bus lines; 
 an interlayer insulating layer formed on the source metal layer; 
 a first transparent conductive layer formed on the interlayer insulating layer; 
 an inorganic insulating layer formed on the first transparent conductive layer; 
 a second transparent conductive layer formed on the inorganic insulating layer; 
 a lower metal layer formed below the gate metal layer; and 
 a lower insulating layer formed between the gate metal layer and the lower metal layer, 
 
 wherein the lower metal layer includes a plurality of CS bus lines each extending in the column direction, the plurality of CS bus lines not overlapping the plurality of source bus lines when viewed in a normal direction of the substrate, and 
 wherein each of the plurality of pixels has
 a drain extension section that is included in the source metal layer and that extends from the first drain electrode, 
 a first transparent electrode included in the first transparent conductive layer, 
 a second transparent electrode that is included in the second transparent conductive layer and is connected to the drain extension section, and 
 an auxiliary capacitor electrode that includes the lower metal layer and/or the gate metal layer, is electrically connected to at least any one of the plurality of CS bus lines, and overlaps the drain extension section when viewed in the normal direction of the substrate. 
 
 
     
     
       2. The active matrix substrate according to  claim 1 ,
 wherein the plurality of CS bus lines are electrically connected to the first transparent conductive layer. 
 
     
     
       3. The active matrix substrate according to  claim 1 ,
 wherein in the lower insulating layer, the gate insulating layer, and the interlayer insulating layer, a plurality of contact holes each reaching any one of the plurality of CS bus lines are formed, and 
 wherein the first transparent conductive layer is in contact with the plurality of CS bus lines in the plurality of contact holes. 
 
     
     
       4. The active matrix substrate according to  claim 3 ,
 wherein the plurality of contact holes include a contact hole formed between the first gate bus line associated with a certain pixel row and the second gate bus line associated with a pixel row adjacent to the certain pixel row. 
 
     
     
       5. The active matrix substrate according to  claim 4 ,
 wherein the plurality of contact holes are provided for every n pixel rows (n is an integer) in the column direction and every 2×n pixel columns in the row direction. 
 
     
     
       6. The active matrix substrate according to  claim 1 ,
 wherein each of the plurality of pixels further has
 a first opening that is formed in the interlayer insulating layer and reaches the drain extension section, and 
 a second opening that is formed in the inorganic insulating layer and overlaps the first opening when viewed in the normal direction of the substrate, and 
 
 wherein the second transparent electrode is in contact with the drain extension section in the first opening. 
 
     
     
       7. The active matrix substrate according to  claim 1 ,
 wherein the drain extension section overlaps any one of the plurality of CS bus lines when viewed in the normal direction of the substrate. 
 
     
     
       8. The active matrix substrate according to  claim 1 ,
 wherein the auxiliary capacitor electrode and/or the plurality of CS bus lines include the lower metal layer and the gate metal layer, and 
 wherein in the auxiliary capacitor electrode, a portion that overlaps the drain extension section when viewed in the normal direction of the substrate includes the gate metal layer. 
 
     
     
       9. The active matrix substrate according to  claim 1 ,
 wherein the auxiliary capacitor electrode includes the lower metal layer and the gate metal layer, 
 wherein each of the plurality of pixels further has a third opening that is formed in the lower insulating layer and reaches the lower metal layer of the auxiliary capacitor electrode, and 
 wherein the gate metal layer of the auxiliary capacitor electrode is formed to cover the third opening. 
 
     
     
       10. The active matrix substrate according to  claim 1 ,
 wherein the plurality of CS bus lines include the lower metal layer and the gate metal layer. 
 
     
     
       11. The active matrix substrate according to  claim 1 , further comprising a second TFT disposed in a region other than the plurality of pixels,
 wherein the second TFT has
 a second semiconductor layer formed on the substrate, 
 the lower insulating layer formed on the second semiconductor layer, 
 a second gate electrode that is included in the gate metal layer and is formed to overlap the second semiconductor layer with the lower insulating layer interposed between the second semiconductor layer and the second gate electrode, 
 the gate insulating layer covering the second gate electrode, and 
 a second source electrode and a second drain electrode that are included in the source metal layer and are connected to the second semiconductor layer. 
 
 
     
     
       12. The active matrix substrate according to  claim 11 ,
 wherein the lower metal layer further includes a lower light shielding section formed to cover at least a channel region of the second semiconductor layer when viewed in the normal direction of the substrate. 
 
     
     
       13. The active matrix substrate according to  claim 11 ,
 wherein the plurality of first TFTs have a first semiconductor layer formed on the gate insulating layer, the first semiconductor layer includes an oxide semiconductor, and the second semiconductor layer includes crystalline silicon. 
 
     
     
       14. A liquid crystal display apparatus comprising:
 the active matrix substrate according to  claim 1 ; 
 a counter substrate disposed to be opposite the active matrix substrate; and 
 a liquid crystal layer provided between the active matrix substrate and the counter substrate. 
 
     
     
       15. The liquid crystal display apparatus according to  claim 14 ,
 wherein the second transparent electrode functions as a pixel electrode, and the counter substrate has a counter electrode opposite the second transparent electrode. 
 
     
     
       16. The liquid crystal display apparatus according to  claim 14 ,
 wherein the second transparent electrode has at least one slit, the second transparent electrode functions as a pixel electrode, and the first transparent electrode functions as a common electrode. 
 
     
     
       17. The active matrix substrate according to  claim 1 ,
 wherein the plurality of CS bus lines extend in parallel with the plurality of source bus lines. 
 
     
     
       18. The active matrix substrate according to  claim 1 ,
 wherein the plurality of CS bus lines extend in the column direction over two or more pixels arranged in the column direction. 
 
     
     
       19. The active matrix substrate according to  claim 6 ,
 wherein each of the plurality of pixels further has a fourth opening that is formed in the first transparent conductive layer and overlaps the first opening when viewed in the normal direction of the substrate, and 
 wherein the first transparent conductive layer is formed on an entire surface of the substrate other than the fourth opening. 
 
     
     
       20. The active matrix substrate according to  claim 1 ,
 wherein the plurality of CS bus lines does not overlap the second transparent electrode when viewed in a normal direction of the substrate.