Vertical transistors with multiple gate lengths

Abstract

A pair of vertical fin field effect transistors (FinFETs) having different gate lengths, includes, a first bottom source/drain on a first region of a substrate, wherein the first bottom source/drain includes a first tier having a first height adjacent to a first vertical fin and a second tier having a second height greater than the first tier removed from the first vertical fin; and a second bottom source/drain on a second region of the substrate, wherein the second bottom source/drain includes a third tier having a third height adjacent to a second vertical fin and a fourth tier having a fourth height greater than the third tier removed from the second vertical fin, wherein the third height is less than the first height and the fourth height is equal to the second height.

What is claimed is: 
     
       1. A method of forming a pair of vertical fin field effect transistors (FinFETs) having different gate lengths, comprising:
 forming a first bottom source/drain on a first region of a substrate adjoining a first vertical fin, wherein the first bottom source/drain has a first offset gap adjacent to the first vertical fin with a height of T 3 ; 
 forming a second bottom source/drain on a second region of the substrate adjacent to a second vertical fin, wherein the second bottom source/drain has a second offset gap adjacent to the second vertical fin with a height of T 1  that is less than T 3 ; 
 forming a first portion of a bottom spacer layer in the first offset gap and a second portion of the bottom spacer layer in the second offset gap; and 
 forming a gate dielectric layer on the first portion of the bottom spacer layer and the second portion of the bottom spacer layer, wherein the gate dielectric layer does not fill in the offset gaps. 
 
     
     
       2. The method of  claim 1 , wherein the difference in height between T 1  and T 3  is in the range of about 1 nm to about 4 nm. 
     
     
       3. The method of  claim 1 , wherein the first offset gap and the second offset gap have a width in the range of about 6 nm to about 18 nm. 
     
     
       4. The method of  claim 3 , wherein the gate dielectric layer has a thickness in the range of about 1 nm to about 3 nm. 
     
     
       5. The method of  claim 4 , further comprising forming a work function layer on the gate dielectric layer, wherein the work function layer fills in the first offset gap and defines a first gate length on the first vertical fin and fills in the second offset gap and defines a second gate length on the second vertical fin. 
     
     
       6. The method of  claim 5 , further comprising forming a conductive gate fill layer on the work function layer. 
     
     
       7. The method of  claim 6 , wherein the first portion and the second portion of the bottom spacer layer are formed by a directional deposition. 
     
     
       8. The method of  claim 6 , wherein the first portion and the second portion of the bottom spacer layer each have a thickness in the range of about 1 nm to about 8 nm. 
     
     
       9. A method of forming a pair of vertical fin field effect transistors (FinFETs) having different gate lengths, comprising:
 forming a first bottom source/drain on a first region of a substrate adjoining a first vertical fin, wherein the first bottom source/drain has a first offset gap adjacent to the first vertical fin with a height of T 3 ; 
 forming a second bottom source/drain on a second region of the substrate adjacent to a second vertical fin, wherein the second bottom source/drain has a second offset gap adjacent to the second vertical fin with a height of T 1  that is less than T 3 ; 
 forming a first portion of a bottom spacer layer in the first offset gap and a second portion of the bottom spacer layer in the second offset gap; 
 forming a first gate structure on the first vertical fin in the first region with a first gate length, Lg 1 ; and 
 forming a second gate structure on the second vertical fin in the seco d region with a second gate length, Lg 2 , wherein the first gate length, Lg 1  is less than the second gate length, Lg 2  due to the difference in the height of T 1  compared to T 3 . 
 
     
     
       10. The method of  claim 9 , further comprising, forming an isolation region in the substrate between the first vertical fin and the second vertical fin. 
     
     
       11. The method of  claim 10 , wherein the isolation region has a width in a range of about 100 nm to about 250 nm. 
     
     
       12. The method of  claim 10 , further comprising forming a first top spacer on the first gate structure and forming a second top spacer on the second gate structure at the same time. 
     
     
       13. The method of  claim 12 , further comprising forming an interlayer dielectric (ILD) layer on the gate structures. 
     
     
       14. The method of  claim 13 , further comprising forming a top source/drain on each of the first vertical fin and the second vertical fin. 
     
     
       15. A method of forming a pair of vertical fin field effect transistors (FinFETs) having different gate lengths, comprising:
 forming an isolation region in a substrate to divide the substrate into a first region and a second region; 
 forming a first bottom source/drain adjoining a first vertical fin on the first region of the substrate, wherein the first bottom source/drain includes a first tier having a first height adjacent to the first vertical fin and a second tier having a second height greater than the first tier; 
 forming a second bottom source/drain adjoining a second vertical fin on the second region of the substrate, wherein the second bottom source/drain includes a third tier having a third height adjacent to the second vertical fin and a fourth tier having a fourth height greater than the third tier. 
 
     
     
       16. The method of  claim 15 , forming a first portion of a bottom spacer layer on the first tier and the second tier and a second portion of the bottom spacer layer on the third tier and the fourth tier. 
     
     
       17. The method of  claim 16 , wherein the first portion and the second portion of the bottom spacer layer are formed by a directional deposition. 
     
     
       18. The method of  claim 16 , forming a gate dielectric layer on the first portion of the bottom spacer layer and the second portion of the bottom spacer layer. 
     
     
       19. The method of  claim 18 , further comprising forming a work function layer on the gate dielectric layer, wherein the work function layer defines a first gate length on the first vertical fin and defines a second gate length on the second vertical fin. 
     
     
       20. The method of  claim 19 , further comprising forming a conductive gate fill layer on the work function layer.