Content addressable memory device

Abstract

A memory device includes a controller circuit, a first stage circuit, and a second stage circuit. The controller circuit outputs a first global pre-charge control signal, a second global pre-charge control signal, and a first local pre-charge control signal. The first stage circuit pre-charges a first global match line according to the first global pre-charge control signal, and to compare search data with first data, in order to determine whether to adjust a first level of the first global match line. The second stage circuit selectively pre-charges a second global match line according to the first level and the second global pre-charge control signal, and determines whether to compare the search data with second data according to a second level of the second global match line and the first local pre-charge control signal, in order to adjust the second level.

What is claimed is: 
     
       1. A memory device, comprising:
 a controller circuit configured to output a first global pre-charge control signal, a second global pre-charge control signal, and a first local pre-charge control signal; 
 a first stage circuit configured to pre-charge a first global match line according to the first global pre-charge control signal, and to compare search data with a plurality of first data, in order to determine whether to adjust a first level of the first global match line; and 
 a second stage circuit configured to selectively pre-charge a second global match line according to the first level and the second global pre-charge control signal, and to determine whether to compare the search data with a plurality of second data according to a second level of the second global match line and the first local pre-charge control signal, in order to adjust the second level. 
 
     
     
       2. The memory device of  claim 1 , wherein the second stage circuit comprises:
 a global pre-charge circuit configured to determine whether to pre-charge the second global match line according to the first level and the second global pre-charge control signal; and 
 a local memory circuit configured to be selectively enabled according to the second level to compare the search data with the plurality of second data according to the first local pre-charge control signal, in order to adjust the second level. 
 
     
     
       3. The memory device of  claim 2 , wherein the global pre-charge circuit comprises:
 a logic gate, wherein when the first stage circuit determines not to adjust the first level according to the search data, the logic gate is configured to output a first control signal according to the second global pre-charge control signal; 
 an inverter configured to output a second control signal according to the first level; 
 a first transistor configured to be turned on according to the first control signal, in order to pre-charge the second global match line; and 
 a second transistor configured to be turned on according to the second control signal, in order to pull down the second level. 
 
     
     
       4. The memory device of  claim 2 , wherein the local memory circuit comprises:
 a local pre-charge circuit configured to determine whether to pre-charge a local match line according to the second level and the first local pre-charge control signal; 
 a plurality of content addressable memory cells configured to store the plurality of second data, and to compare the search data with the plurality of second data, in order to determine whether to adjust a third level of the local match line; and 
 a protection circuit configured to adjust the second level according to the third level and a second local pre-charge control signal, and to provide a leakage protection to the second global match line. 
 
     
     
       5. The memory device of  claim 4 , wherein the local pre-charge circuit comprises:
 a logic gate, wherein when the second stage circuit pre-charges the second global match line, the logic gate is configured to generate a control signal according to the first local pre-charge control signal; and 
 a transistor configured to be turned on according to the control signal, in order to pre-charge the local match line. 
 
     
     
       6. The memory device of  claim 4 , wherein the protection circuit comprises:
 a first transistor; 
 a second transistor, wherein the first transistor and the second transistor are configured to operate as an inverter, and to generate a control signal according to the third level; 
 a third transistor coupled between the second transistor and ground, and configured to be selectively turned on according to the second level; 
 a fourth transistor configured to be selectively turned on according to the control signal; and 
 a fifth transistor coupled to the fourth transistor and ground, and configured to be selectively turned on according to the second local pre-charge control signal, wherein the fourth transistor is coupled between the second global match line and the fifth transistor. 
 
     
     
       7. The memory device of  claim 4 , wherein the first local pre-charge control signal is inversed to the second local pre-charge control signal. 
     
     
       8. The memory device of  claim 4 , wherein when the search data is not matched with the plurality of first data, the local pre-charge circuit does not pre-charge the local match line. 
     
     
       9. The memory device of  claim 2 , wherein when the search data is not matched with the plurality of second data, the local memory circuit pulls down the second level. 
     
     
       10. The memory device of  claim 2 , wherein when the search data is matched with the plurality of second data, the local memory circuit keeps the second level. 
     
     
       11. The memory device of  claim 1 , wherein the first stage circuit comprises:
 a global pre-charge circuit configured to pre-charge the first global match line according to the first global pre-charge control signal; and 
 a local memory circuit configured to store the plurality of first data, and to compare the search data with the plurality of first data, in order to determine whether to adjust the first level. 
 
     
     
       12. The memory device of  claim 11 , wherein when the search data is not matched with the first data, the local memory circuit pulls down the first level. 
     
     
       13. The memory device of  claim 11 , wherein when the search data is matched with the first data, the local memory circuit keeps the first level. 
     
     
       14. The memory device of  claim 1 , wherein when the first stage circuit compares the search data with the plurality of first data, the second stage circuit selectively pre-charges the second global match line. 
     
     
       15. The memory device of  claim 1 , wherein a time interval when the first global match line is pre-charged is different from a time interval when the second global match line is pre-charged. 
     
     
       16. The memory device of  claim 1 , wherein a time interval when the first stage circuit compares the search data with the plurality of first data is different from a time interval when the second stage circuit compares the search data with the plurality of second data. 
     
     
       17. The memory device of  claim 1 , wherein when the second stage circuit compares the search data with the plurality of second data, the first stage circuit pre-charges the first global match line. 
     
     
       18. The memory device of  claim 1 , wherein when the search data is not matched with the plurality of first data, the second stage circuit does not pre-charge the second global match line.