Image processing chip test method

Abstract

An image processing chip test method comprising: controlling a power supply circuit to provide a first operating voltage to an image processing chip comprising a storage device; and when reading written first image data from the storage device, the test device receives a first error detection code corresponding to the first image data and determines whether the first error detection code means an error occurs. If an error occurs, record the first operating voltage as an erroneous operating voltage, and if the error does not occur, provide a second operating voltage to the image processing chip. Also, when the written second image data is read from the storage device, the test device receives a second error detection code corresponding to the second image data and determines whether the second error detection code means an error occurs.

What is claimed is: 
     
       1. An image processing chip test method performed by executing at least one program on a test device, comprising:
 controlling a power supply circuit to provide a first operating voltage to an image processing chip comprising at least one storage device; 
 writing first image data to the storage device; 
 receiving a first error detection code corresponding to the first image data and determining whether the first error detection code means an error occurs by the test device, while reading the first image data from the storage device; 
 recording the first operating voltage as the erroneous operating voltage, when the first error detection code means the error occurs; and 
 providing a second operating voltage to the image processing chip, writing second image data to the storage device, reading the second image from the storage device, receiving a second error detection code corresponding to the second image data and determining whether the second error detection code means the error occurs, when the first error detection code means that the error does not occur. 
 
     
     
       2. The image processing chip test method of  claim 1 , wherein the second operating voltage is lower than the first operating voltage. 
     
     
       3. The image processing chip test method of  claim 2 , further comprising:
 recording the second operating voltage as the erroneous operating voltage, when the second error detection code means the error occurs; and 
 providing a third operating voltage to the image processing chip, writing third image data to the storage device, and reading the third image from the storage device, receiving a third error detection code corresponding to the third image data and determining whether the third error detection code means the error occurs, when the second error detection code means the error does not occur; 
 wherein the third operating voltage is lower than the second operating voltage. 
 
     
     
       4. The image processing chip test method of  claim 1 , wherein the second operating voltage is higher than the first operating voltage, and the first operating voltage is a lowest voltage at which the image processing chip can operate normally. 
     
     
       5. The image processing chip test method of  claim 4 , further comprising:
 recording the second operating voltage as the erroneous operating voltage, when the second error detection code means the error occurs; and 
 providing a third operating voltage to the image processing chip, writing third image data to the storage device, and reading the third image from the storage device, receiving a third error detection code corresponding to the third image data and determining whether the third error detection code means the error occurs, when the second error detection code means the error does not occur; 
 wherein the third operating voltage is higher than the second operating voltage. 
 
     
     
       6. The image processing chip test method of  claim 1 , wherein the first error detection code is a CRC (cyclic redundancy check) code. 
     
     
       7. The image processing chip test method of  claim 6 , wherein the storage device is a DDR (double data rate) memory. 
     
     
       8. The image processing chip test method of  claim 1 ,
 wherein the image processing chip further comprises a display driving circuit coupled to the storage device, the display driving circuit is coupled to a display to control the display to display image data read from the storage device; 
 wherein the display displays a corresponding defected screen when the error detection code means the error occurs. 
 
     
     
       9. The image processing chip test method of  claim 1 , further comprising a display driving circuit independent from the image processing chip and coupled to the storage device, the display driving circuit is coupled to a display to control the display to display image data read by the storage device;
 wherein the display displays a corresponding defected screen when the error detection code means the error occurs. 
 
     
     
       10. The image processing chip test method of  claim 1 , wherein the first image data and the second image data comprise identical image content. 
     
     
       11. An image processing chip test system, comprising:
 a test device; 
 a power supply circuit; and 
 an image processing chip, comprising at least one storage device; 
 wherein the test device controls a power supply circuit to provide a first operating voltage to an image processing chip; 
 wherein the test device receives a first error detection code corresponding to the first image data and determines whether the first error detection code means an error occurs by the test device, while first image data is read from the storage device; 
 wherein the test device records the first operating voltage as the erroneous operating voltage, when the first error detection code means the error occurs; 
 wherein the test device controls the power supply circuit to provide a second operating voltage to the image processing chip, when the first error detection code means that the error does not occur; and 
 wherein the test device receives a second error detection code corresponding to second image data and determining whether the second error detection code means the error occurs when second image is read from the storage device, when the first error detection code means that the error does not occur. 
 
     
     
       12. The image processing chip test system of  claim 11 , wherein the second operating voltage is lower than the first operating voltage. 
     
     
       13. The image processing chip test system of  claim 12 , further comprising:
 wherein the test device records the second operating voltage as the erroneous operating voltage, when the second error detection code means the error occurs; and 
 wherein the test device controls the power supply circuit to provide a third operating voltage to the image processing chip, when the second error detection code means that the error does not occur; 
 wherein the test device receives a third error detection code corresponding to third image data and determines whether the third error detection code means the error occurs when third image is read from the storage device, when the second error detection code means that the error does not occur; 
 wherein the third operating voltage is lower than the second operating voltage. 
 
     
     
       14. The image processing chip test system of  claim 11 , wherein the second operating voltage is higher than the first operating voltage, and the first operating voltage is a lowest voltage at which the image processing chip can operate normally. 
     
     
       15. The image processing chip test system of  claim 14 , further comprising:
 wherein the test device records the second operating voltage as the erroneous operating voltage, when the second error detection code means the error occurs; and 
 wherein the test device controls the power supply circuit to provide a third operating voltage to the image processing chip, when the second error detection code means that the error does not occur; 
 wherein the test device receives a third error detection code corresponding to third image data and determines whether the third error detection code means the error occurs when third image is read from the storage device, when the second error detection code means that the error does not occur; 
 wherein the third operating voltage is higher than the second operating voltage. 
 
     
     
       16. The image processing chip test system of  claim 11 , wherein the first error detection code is a CRC (cyclic redundancy check) code. 
     
     
       17. The image processing chip test system of  claim 16 , wherein the storage device is a DDR (double data rate) memory. 
     
     
       18. The image processing chip test system of  claim 11 ,
 wherein the image processing chip further comprises a display driving circuit coupled to the storage device, the display driving circuit is coupled to a display to control the display to display image data read from the storage device; 
 wherein the display displays a corresponding defected screen when the error detection code means the error occurs. 
 
     
     
       19. The image processing chip test system of  claim 11 , further comprising a display driving circuit independent from the image processing chip and coupled to the storage device, the display driving circuit is coupled to a display to control the display to display image data read by the storage device;
 wherein the display displays a corresponding defected screen when the error detection code means the error occurs. 
 
     
     
       20. The image processing chip test system of  claim 11 , wherein the first image data and the second image data comprise identical image content.