Time synchronization of distributed devices

Abstract

A method and system of synchronizing a local clock with a master clock using a serial communication bus includes receiving by a serial data interface receiver a master time signal corresponding to a master clock, generating by a frequency tuning loop a time error signal corresponding to a difference between the master time signal and a local time signal, generating by the frequency tuning loop an actual frequency signal based on a base frequency and the time error signal, producing by the frequency tuning loop a command frequency error based on the actual frequency signal and the local time signal, and producing by the local clock an updated local time signal based on the command frequency error.

The invention claimed is: 
     
       1. A method of synchronizing a local clock with a master clock using a serial communication bus, the method comprising:
 receiving, by a serial data interface receiver, a master time signal corresponding to a master clock; 
 generating, by a frequency tuning loop, a time error signal corresponding to a difference between the master time signal and a local time signal, wherein the time error signal is generated at a predetermined interval; 
 generating, by the frequency tuning loop, an actual frequency signal based on:
 a base frequency, the predetermined interval, and the time error signal; 
 
 producing, by the frequency tuning loop, a command frequency error based on the actual frequency signal and the local time signal; and 
 producing, by the local clock, an updated local time signal based on the command frequency error. 
 
     
     
       2. The method of  claim 1 , further comprising producing, by a time error amplifier, a frequency error signal, wherein the frequency error signal is representative of the time error signal. 
     
     
       3. The method of  claim 1 , further comprising producing, by an oscillator, the local time signal, wherein:
 the oscillator defines an oscillator frequency; and 
 the local time signal is representative of the oscillator frequency. 
 
     
     
       4. The method of  claim 3 , further comprising producing, by a feedback optimizing component, an oscillator control signal, wherein the feedback optimizing component is configured to reduce overshoot and/or undershoot by the oscillator. 
     
     
       5. The method of  claim 4 , wherein the feedback optimizing component comprises one or more of: a proportional component, an integrating component, and a differentiating component. 
     
     
       6. The method of  claim 5 , wherein the feedback optimizing component comprises a proportional integral derivative controller. 
     
     
       7. The method of  claim 3 , wherein the oscillator frequency ranges from 1 MHz —1 GHz. 
     
     
       8. The method of  claim 7 , wherein the oscillator frequency ranges from 10 MHz —100 MHz. 
     
     
       9. The method of  claim 3 , wherein the oscillator is selected from the group consisting of a digitally-controlled crystal oscillator and a voltage-controlled crystal oscillator. 
     
     
       10. The method of  claim 1 , further comprising transmitting, by a serial data interface transmitter, the updated local time signal, wherein the updated local time signal is synchronized with the master time signal. 
     
     
       11. The method of  claim 1 , wherein a time-keeping difference between the local clock and the master clock is less than 1 microsecond. 
     
     
       12. The method of  claim 1 , wherein the serial communication bus uses a serial communication protocol that is selected from the group consisting of: RS-485, RS-422, RS-232, controller area network (CAN), local interconnect network (LIN), optical link, and wireless link. 
     
     
       13. The method of  claim 12 , wherein:
 the serial communication protocol is RS-485; and 
 the serial data interface receiver is an RS-485 receiver. 
 
     
     
       14. The method of  claim 1 , wherein:
 the master clock is disposed on a master controller; and 
 the local clock is disposed on a sub-controller. 
 
     
     
       15. A system for synchronizing a local clock with a master clock using a serial communication bus, the system comprising:
 a serial data interface receiver, configured to receive a master time signal corresponding to the master clock; 
 a frequency tuning loop, configured to:
 generate a time error signal corresponding to a difference between the master time signal and a local time signal, wherein the time error signal is generated at a predetermined interval; 
 generate an actual frequency signal based on:
 a base frequency, the predetermined interval, and 
 the time error signal; 
 
 produce a command frequency error based on the actual frequency signal and the local time signal; and 
 produce an updated local time signal based on the command frequency error; 
 
 wherein the updated local time signal is representative of the local clock. 
 
     
     
       16. The system of  claim 15 , wherein a time-keeping difference between the local clock and the master clock is less than 1 microsecond. 
     
     
       17. The system of  claim 15 , wherein the time-keeping difference between the local clock and the master clock is less than 100 nanoseconds. 
     
     
       18. A distributed device network, comprising:
 a serial communication bus; 
 a master controller; 
 a master clock, disposed on the master controller; and 
 one or more sub-controllers, each comprising:
 a local clock; 
 a serial data interface receiver, configured to receive a master time signal corresponding to the master clock; 
 a frequency tuning loop, configured to:
 generate a time error signal corresponding to a difference between the master time signal and a local time signal, wherein the time error signal is generated at a predetermined interval; 
 generate an actual frequency signal based on:
 a base frequency, the predetermined interval, and 
 the time error signal; 
 
 produce a command frequency error based on the actual frequency signal and the local time signal; and 
 produce an updated local time signal based on the command frequency error; 
 wherein the updated local time signal is representative of the local clock. 
 
 
 
     
     
       19. The distributed device network of  claim 18 , further comprising one or more nodes, each of the one or more nodes comprising a node clock, wherein:
 each of the one or more nodes is connected to an associated sub-controller by a serial communication bus; and 
 each of the one or more nodes is configured to provide time synchronization between a respective local clock of the associated sub-controller and the respective node clock using the serial communication bus. 
 
     
     
       20. The distributed device network of  claim 19 , wherein the distributed device network is a smart sensing system.