US11156692B2ActiveUtilityA1
Calibrating differential measurement circuitry
Est. expiryFeb 19, 2040(~13.6 yrs left)· nominal 20-yr term from priority
Inventors:Igor Golger
H03F 2203/45528H03F 2203/45151H03F 2203/45048H03F 3/45475G01R 35/007G01R 31/2834G01R 35/005H03M 1/12H03F 3/45H03M 1/1023
38
PatentIndex Score
0
Cited by
17
References
21
Claims
Abstract
Example circuitry includes a first circuit to provide a low signal; a second circuit to provide a high signal, where the high signal has a greater voltage magnitude than the low signal; and a differential amplifier configured to receive the low signal from the first circuit and the high signal from the second circuit. The differential amplifier is for producing an output voltage that is based on the high signal and the low signal. The example circuitry includes a first measurement circuit to measure the output voltage; a second measurement circuit to measure the low signal at the first circuit; and processing logic to determine a differential measurement based on the output voltage measured by the first measurement circuit, the low signal measured by the second measurement circuit, and calibration values obtained for the circuitry.
Claims
exact text as granted — not AI-modifiedWhat is claimed is:
1. Circuitry comprising:
a first circuit to provide a low signal;
a second circuit to provide a high signal, the high signal having a greater voltage magnitude than the low signal;
a differential amplifier configured to receive the low signal from the first circuit and the high signal from the second circuit, the differential amplifier for producing an output voltage that is based on the high signal and the low signal;
a first measurement circuit to measure the output voltage;
a second measurement circuit to measure the low signal at the first circuit; and
processing logic to determine a differential measurement based on the output voltage measured by the first measurement circuit, the low signal measured by the second measurement circuit, and calibration values obtained for the circuitry.
2. The circuitry of claim 1 , wherein the processing logic is configured to determine the differential measurement (hs−ls) as follows
(
h
s
-
l
s
)
=
V
o
G
H
-
l
s
(
m
)
*
G
H
+
G
L
G
H
-
Ofs
G
H
where Vo is the output voltage measured by the first measurement circuit, ls(m) is the low signal measured by the second measurement circuit, GH and GL are the calibration values, and Ofs is an offset value produced when the low signal and the high signal are at or near zero volts (0V).
3. The circuitry of claim 2 , wherein GH is a positive value and GL is a negative value that is different from GH, where a difference between absolute values of GH and GL is 10% or less.
4. The circuitry of claim 2 , wherein GH is a positive value and GL is a negative value that is different from GH, where a difference between absolute values of GH and GL is 5% or less.
5. The circuitry of claim 2 , wherein an absolute value of ls(m) is 200 mV or less.
6. The circuitry of claim 2 , wherein GH is a value that is determined by connecting the first circuit to electrical ground and by connecting the second circuit to a known voltage.
7. The circuitry of claim 2 , wherein GH+GL is a value that is determined by connecting the first circuit and the second circuit together and applying known voltage to the first circuit and the second circuit connected together.
8. The circuitry of claim 2 , wherein GH and GL are determined separately from each other.
9. The circuitry of claim 1 , wherein the first measurement circuit comprises a first analog-to-digital converter (ADC), the second measurement circuit comprises a second ADC, and the second ADC has a lower accuracy than a final measurement specification for the circuitry.
10. The circuitry of claim 1 , wherein the first measurement circuit comprises a first analog-to-digital converter (ADC), the second measurement circuit comprises a second ADC, and the first ADC is more accurate than the second ADC.
11. The circuitry of claim 1 , wherein the differential amplifier includes resistors on a feedback path and a feedforward path, the output voltage being based, at least in part, on values of the resistors.
12. The circuitry of claim 1 , wherein the processing logic comprises one or more microprocessors.
13. The circuitry of claim 1 , wherein the processing logic comprises programmable logic.
14. The circuitry of claim 1 , wherein the circuitry is part of a ground re-referencing circuit.
15. Automatic test equipment (ATE) comprising:
a circuit board to connect to a device under test (DUT), the DUT being connected to a first electrical reference on the circuit board; and
test circuitry connected to a second electrical reference, the second electrical reference being at a different voltage than the first electrical reference which causes a pair of signals output from the DUT to the test circuitry to change voltage values while maintaining a constant voltage difference;
wherein the test circuitry comprises:
a first circuit to provide a low signal in the pair of signals;
a second circuit to provide a high signal in the pair of signals, the high signal having a greater voltage magnitude than the low signal;
a differential amplifier configured to receive the low signal from the first circuit and the high signal from the second circuit, the differential amplifier for producing an output voltage that is based on a difference between the high signal and the low signal;
a first measurement circuit to measure the output voltage;
a second measurement circuit to measure the low signal at the first circuit; and
processing logic to determine a differential measurement based on the output voltage measured by the first measurement circuit, the low signal measured by the second measurement circuit, and calibration values obtained for the test circuitry.
16. The ATE of claim 15 , further comprising a test instrument for performing one or more tests on the DUT, the test circuitry being part of the test instrument.
17. The ATE of claim 16 , wherein the first electrical reference is a first electrical ground for the DUT and the second electrical reference is a second electrical ground for the test circuitry.
18. The ATE of claim 15 , wherein the processing logic is configured to determine the differential measurement (hs−ls) as follows
(
h
s
-
l
s
)
=
V
o
G
H
-
l
s
(
m
)
*
G
H
+
G
L
G
H
-
Ofs
G
H
where Vo is the output voltage measured by the first measurement circuit, ls(m) is the low signal measured by the second measurement circuit, GH and GL are calibration values, and Ofs is an offset value produced when the low signal and the high signal are at or near zero volts (0V).
19. The ATE of claim 18 , wherein the first measurement circuit comprises a first analog-to-digital converter (ADC), the second measurement circuit comprises a second ADC, and the second ADC has a lower accuracy than a final measurement specification for the test circuitry.
20. The ATE of claim 18 , wherein the first measurement circuit comprises a first analog-to-digital converter (ADC), the second measurement circuit comprises a second ADC, and the first ADC is more accurate than the second ADC.
21. The ATE of claim 18 , wherein GH is a positive value and GL is a negative value that is different from GH, where a difference between absolute values of GH and GL is 5% or less.Join the waitlist — get patent alerts
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