Fully-depleted CMOS transistors with u-shaped channel

Abstract

A structure capable of effectively preventing dopant diffusion from source/drain regions into an underlying semiconductor-on-insulator (SOI) layer of fully-depleted SOI transistors with U-shaped channels is provided. By inserting a dopant diffusion barrier layer between an SOI layer of an SOI substrate and a doped extension layer from which source/drain extension regions are derived, the undesired dopant diffusion from the source/drain extension regions into the underlying SOI layer can be prevented.

What is claimed is: 
     
       1. A method of forming a semiconductor structure comprising:
 forming a dopant diffusion barrier layer over a semiconductor-on-insulator (SOI) layer of an SOI substrate; 
 forming a doped extension layer over the dopant diffusion barrier layer; 
 forming a sacrificial gate structure over a portion of the doped extension layer, the sacrificial gate structure comprising a sacrificial gate stack and a gate spacer present on sidewalls of the sacrificial gate stack, wherein the gate spacer has a surface that is in direct physical contact with a surface of the doped extension layer; 
 forming, after forming the sacrificial gate structure, raised source/drain regions over portions of the doped extension layer that are not covered by the sacrificial gate structure wherein the raised source/drain regions have a sidewall edge that is in direct physical contact with a sidewall of the gate spacer; 
 forming an interlevel dielectric (ILD) layer on the raised source/drain regions and laterally surrounding the sacrificial gate structure; 
 removing the sacrificial gate stack to form a gate cavity, wherein the gate cavity physically exposes a portion of the doped extension layer; 
 removing the physically exposed portion of the doped extension layer, a portion of the dopant diffusion barrier layer and a portion of the SOI layer to provide an opening underneath the gate cavity, wherein the opening extends through the doped extension layer and the dopant diffusion barrier layer and partially into the SOI layer to expose a recessed surface of the SOI layer at a bottom of the opening; and 
 forming a functional gate stack in the gate cavity and the opening. 
 
     
     
       2. The method of  claim 1 , wherein the dopant diffusion barrier layer comprises carbon doped silicon. 
     
     
       3. The method of  claim 2 , wherein the carbon doped silicon has a carbon concentration of from 0.1 atomic percent to 2 atomic percent. 
     
     
       4. The method of  claim 1 , wherein the doped extension layer is composed of boron doped SiGe. 
     
     
       5. The method of  claim 1 , wherein the doped extension layer is composed of phosphorus doped Si. 
     
     
       6. The method of  claim 1 , wherein the doped extension layer has a dopant concentration greater than 1×10 20  atoms/cm 3 . 
     
     
       7. The method of  claim 1 , wherein a thinned portion of the SOI layer located beneath the opening has a thickness ranging from 3 nm to 10 nm. 
     
     
       8. The method of  claim 1 , wherein the SOI layer has a thickness ranging from 8 nm to 20 nm. 
     
     
       9. The method of  claim 1 , further comprising recessing the portions of the doped extension layer that are not covered by the sacrificial gate structure prior to the forming the raised source/drain regions, wherein the raised source/drain regions contact recessed surfaces of the doped extension layer. 
     
     
       10. The method of  claim 1 , wherein the functional gate structure comprises a U-shaped gate dielectric and a gate electrode overlying the U-shaped gate dielectric. 
     
     
       11. The method of  claim 10 , wherein the forming the functional gate structure comprises:
 forming a gate dielectric layer on a bottom surface and sidewalls of the opening, sidewalls of the gate cavity and a top surface of the ILD layer; 
 forming a gate electrode layer to completely fill the gate cavity and opening; and 
 removing portions of the gate electrode layer and the gate dielectric layer from the top surface the ILD layer. 
 
     
     
       12. The method of  claim 10 , wherein remaining portions of each of the dopant diffusion barrier layer and the doped extension layer directly contact vertical portions of the U-shaped gate dielectric. 
     
     
       13. The method of  claim 1 , wherein the raised source/drain regions are composed of a semiconductor material comprising a dopant that has a same conductivity as a dopant present in the doped extension layer. 
     
     
       14. The method of  claim 1 , wherein the forming the raised source/drain regions comprises a selective epitaxy. 
     
     
       15. The method of  claim 1 , wherein the ILD layer has a topmost surface that is coplanar with a topmost surface of the sacrificial gate structure. 
     
     
       16. The method of  claim 1 , wherein the removing of the sacrificial gate stack comprises an ammonia etch. 
     
     
       17. The method of  claim 1 , wherein the gate cavity is confined by inner sidewalls of the gate spacer. 
     
     
       18. The method of  claim 1 , wherein the removing the physically exposed portion of the doped extension layer, the portion of the dopant diffusion barrier layer and the portion of the SOI layer comprises an anisotropic etch. 
     
     
       19. A method of forming a semiconductor structure comprising:
 forming a dopant diffusion barrier layer over a semiconductor-on-insulator (SOI) layer of an SOI substrate; 
 forming a doped extension layer over the dopant diffusion barrier layer; 
 forming a sacrificial gate structure over a portion of the doped extension layer, the sacrificial gate structure comprising a sacrificial gate stack and a gate spacer present on sidewalls of the sacrificial gate stack; 
 forming raised source/drain regions over portions of the doped extension layer that are not covered by the sacrificial gate structure, wherein the portions of the doped extension layer that are not covered by the sacrificial gate structure are recessed prior to the forming the raised source/drain regions, and wherein the raised source/drain regions contact a recessed surface of the doped extension layer; 
 forming an interlevel dielectric (ILD) layer over the raised source/drain regions to laterally surround the sacrificial gate structure; 
 removing the sacrificial gate stack to form a gate cavity; 
 removing portions of the doped extension layer, the dopant diffusion barrier layer and the SOI layer to provide an opening underneath the gate cavity, wherein the opening extends through the doped extension layer and the dopant diffusion barrier layer and partially into the SOI layer to expose a recessed surface of the SOI layer at a bottom of the opening; and 
 forming a functional gate stack in the gate cavity and the opening, wherein the raised source/drain regions are composed of a semiconductor material comprising a dopant that has a same conductivity as a dopant present in the doped extension layer, and wherein the semiconductor material that provides the raised source/drain regions is a compositionally same semiconductor material as a semiconductor material that provides the doped extension layer. 
 
     
     
       20. A method of forming a semiconductor structure comprising:
 forming a dopant diffusion barrier layer over a semiconductor-on-insulator (SOI) layer of an SOI substrate; 
 forming a doped extension layer over the dopant diffusion barrier layer; 
 forming a sacrificial gate structure over a portion of the doped extension layer, the sacrificial gate structure comprising a sacrificial gate stack and a gate spacer present on sidewalls of the sacrificial gate stack; 
 forming raised source/drain regions over portions of the doped extension layer that are not covered by the sacrificial gate structure, wherein the portions of the doped extension layer that are not covered by the sacrificial gate structure are recessed prior to the forming the raised source/drain regions, and wherein the raised source/drain regions contact a recessed surface of the doped extension layer; 
 forming an interlevel dielectric (ILD) layer over the raised source/drain regions to laterally surround the sacrificial gate structure; 
 removing the sacrificial gate stack to form a gate cavity; 
 removing portions of the doped extension layer, the dopant diffusion barrier layer and the SOI layer to provide an opening underneath the gate cavity, wherein the opening extends through the doped extension layer and the dopant diffusion barrier layer and partially into the SOI layer to expose a recessed surface of the SOI layer at a bottom of the opening; and 
 forming a functional gate stack in the gate cavity and the opening, wherein the raised source/drain regions are composed of a semiconductor material comprising a dopant that has a same conductivity as a dopant present in the doped extension layer, and wherein the semiconductor material that provides the raised source/drain regions is a compositionally different semiconductor material than a semiconductor material that provides the doped extension layer.