US11132305B1ActiveUtility

Automatic static region generation for memory protection units (MPUs)

Assignee: MOORE RALPH CRITTENDENPriority: Jun 11, 2020Filed: Jun 11, 2020Granted: Sep 28, 2021
Est. expiryJun 11, 2040(~13.9 yrs left)· nominal 20-yr term from priority
G06F 8/453G06F 12/0284G06F 2212/1052G06F 12/1441G06F 8/41G06F 12/1433G06F 12/0246
83
PatentIndex Score
2
Cited by
5
References
6
Claims

Abstract

This invention presents a method for error-free, automatic generation of regions for Memory Protection Units (MPUs) to ease development of systems, using MPUs.

Claims

exact text as granted — not AI-modified
The invention claimed is: 
     
       1. Method to automatically generate regions for memory protection units, which can be loaded with a multiplicity of said regions, each controlling access to a specified memory or input-output area, and where each said region consists of a starting address, a size, and subregion disables, and said subregion disables disable subregions not needed by said region so that their memory areas can be used in other regions, as follows:
 defining sectors consisting of contiguous code or data in the source code and grouping like said sectors into region blocks; 
 defining the smallest region size, which is a power of two times the smallest permitted region size, that said region block will fit into and assigning said region size to be the alignment of said region block; 
 defining the smallest region size that said region block will fit into as said region size times a fraction where said fraction equals a subregion number divided by the number of subregions per region and where said subregion number is greater than one half of the said number of subregions per said region; 
 using a macro in said source code that finds said subregion number such that said region block size modulo said subregion number is 0 and said macro uses said subregion number to generate said subregion disables for said region. 
 
     
     
       2. The method of  claim 1  wherein said region block is defined in a linker command file from which a linker provides said region block size to a compiler, which evaluates said macro with said region block size to determine said subregion disables. 
     
     
       3. The method of  claim 2  wherein said region is thus automatically generated by said compiler and thus is free from possible programmer error. 
     
     
       4. The method of  claim 2  wherein said region can be assigned by said linker to read-only memory in order to protect it from change by a hacker. 
     
     
       5. The method of  claim 1  wherein gaps due to alignments of said region blocks are filled by placing smaller said region blocks between them. 
     
     
       6. The method of  claim 5  wherein non-region blocks of various sizes are defined in said linker command file to help plug said gaps between said aligned region blocks.

Join the waitlist — get patent alerts

Track US11132305B1 — get alerts on status changes and closely related new filings.

We store only your email — no account needed. See our privacy policy.