Cache control in a parallel processing system

Abstract

Method and apparatus are disclosed for cache control in a parallel processing system. The apparatus includes a plurality of application specific engines configured to generate a plurality of commands, a cache array configured to store the plurality of commands, and a cache command controller configured to receive a command asynchronously from an application specific engine in the plurality of application specific engines, update the cache array to include the received command, and validate the updated cache array while maintaining parallel accessing of the cache array by the plurality of application specific engines.

What is claimed is: 
     
       1. An apparatus for controlling cache commands in a parallel processing system, comprising:
 a plurality of application specific engines configured to generate a plurality of commands; 
 a cache array configured to store the plurality of commands; and 
 a cache command controller configured to 
 receive a command asynchronously from an application specific engine in the plurality of application specific engines, 
 update the cache array to include the received command, and 
 validate the updated cache array while maintaining parallel accessing of the cache array by the plurality of application specific engines. 
 
     
     
       2. The apparatus of  claim 1 , wherein a command in the plurality of commands includes a command header descriptor, and wherein the command header descriptor comprises:
 an index configured to indicate a location of the entry in the cache array; 
 a validity bit configured to indicate whether the entry is valid; 
 a length field configured to indicate a length of the entry; and 
 a logical block address configured to indicate a starting address of the entry. 
 
     
     
       3. The apparatus of  claim 1 , further comprising:
 a command arbitrator configured to select the received command from the plurality of application specific engines for processing. 
 
     
     
       4. The apparatus of  claim 1 , wherein the plurality of commands comprises at least one of:
 one or more host commands received via a host interface; or 
 one or more recycle commands, retrieved from a recycle queue, configured to identify a NAND block of a solid-state drive for recycle. 
 
     
     
       5. The apparatus of  claim 1 , wherein the cache command controller is further configured to:
 search the cache array to identify an empty entry to store the received command; and 
 insert the received command to the empty entry in the cache array. 
 
     
     
       6. The apparatus of  claim 5 , wherein the cache command controller is further configured to:
 scan the cache array to record valid entries and full entries; and 
 skip valid entries and full entries during the search of the cache array. 
 
     
     
       7. The apparatus of  claim 1 , wherein the cache command controller is further configured to:
 in response to updating the cache array with the received command, 
 activate a cache validation checker to validate the received command in the updated cache array; and 
 upon updating the cache array with the received command, set a status bit associated with a cache entry to be valid. 
 
     
     
       8. The apparatus of  claim 7 , wherein the cache command controller is further configured to:
 upon completion of executing the received command, remove the received command from the cache array by setting a status bit associated with a cache entry of the received command to be invalid. 
 
     
     
       9. The apparatus of  claim 1 , wherein the cache command controller is further configured to:
 loop through entries in the cache array, 
 examine entries of the cache array in a wrapped around manner; 
 detect data range of the received command with respect to commands from the entries of the cache array; 
 identify related command pairs based on the data range of the received command with respect to the commands; and 
 store the related command pairs in an output queue. 
 
     
     
       10. The apparatus of  claim 9 , wherein the cache command controller is further configured to:
 scan the cache array to record empty entries; 
 determine a skip count based on a number of empty entries to be skipped; and 
 skip consecutive empty entries by the cache validation checker based on the skip count. 
 
     
     
       11. The apparatus of  claim 9 , wherein an entry in the related command pairs output queue comprises:
 an index of the received command; 
 an index of an existing command; and 
 a status of relationships between the received command and the existing command. 
 
     
     
       12. The apparatus of  claim 9 , wherein the cache command controller is further configured to:
 resolve overlapping commands using time stamps and command identifiers from an event page array, wherein the event page array is correlated to the received command with a same index array; 
 re-order the overlapping commands using time stamps from the event page; and 
 ignore duplicate commands based on indexes of the overlapping commands being the same. 
 
     
     
       13. A method of cache control in a parallel processing system, comprising:
 generating, by an application engine in a plurality of application specific engines, a command; 
 receive, by a cache command controller, the command asynchronously from the application specific engine in the plurality of application specific engines; 
 updating, by the cache command controller, a cache array to include the received command; and 
 validating, by the cache command controller, the updated cache array while maintaining parallel accessing of the cache array by the plurality of application specific engines. 
 
     
     
       14. The method of  claim 13 , wherein a command in the plurality of commands includes a command header descriptor, and wherein the command header descriptor comprises:
 an index configured to indicate a location of the entry in the cache array; 
 a validity bit configured to indicate whether the entry is valid; 
 a length field configured to indicate a length of the entry; and 
 a logical block address configured to indicate a starting address of the entry. 
 
     
     
       15. The method of  claim 13 , further comprising:
 selecting, by a command arbitrator, the received command from the plurality of application specific engines for processing. 
 
     
     
       16. The method of  claim 13 , wherein the plurality of commands comprises at least one of:
 one or more host commands received via a host interface; or 
 one or more recycle commands, retrieved from a recycle queue, configured to identify a NAND block of a solid-state drive for recycle. 
 
     
     
       17. The method of  claim 13 , wherein updating the cache array to include the received command comprises:
 searching the cache array to identify an empty entry to store the received command; and 
 inserting the received command to the empty entry in the cache array. 
 
     
     
       18. The method of  claim 17 , wherein searching the cache array to identify the empty entry comprises:
 scanning the cache array to record valid entries and full entries; and 
 skipping valid entries and full entries during the search of the cache array. 
 
     
     
       19. The method of  claim 13 , further comprising:
 in response to updating the cache array with the received command, 
 activating a cache validation checker to validate the received command in the updated cache array; and 
 upon updating the cache array with the received command, setting a status bit associated with a cache entry to be valid. 
 
     
     
       20. The method of  claim 19 , further comprising:
 upon completion of executing the received command, removing the received command from the cache array by setting a status bit associated with a cache entry of the received command to be invalid. 
 
     
     
       21. The method of  claim 19 , wherein activating the cache validation checker to validate the received command in the updated cache array comprises:
 looping through entries in the cache array, 
 examining entries of the cache array in a wrapped around manner; 
 detecting data range of the received command with respect to commands from the entries of the cache array; 
 identifying related command pairs based on the data range of the received command with respect to the commands; and 
 storing the related command pairs in an output queue. 
 
     
     
       22. The method of  claim 21 , wherein examining entries of the cache array further comprising:
 scanning the cache array to record empty entries; 
 determining a skip count based on a number of empty entries to be skipped; and 
 skipping consecutive empty entries by the cache validation checker based on the skip count. 
 
     
     
       23. The method of  claim 21 , wherein an entry in the related command pairs output queue comprises:
 an index of the received command; 
 an index of an existing command; and 
 a status of relationships between the received command and the existing command. 
 
     
     
       24. The method of  claim 21 , further comprising:
 resolving overlapping commands using time stamps and command identifiers from an event page array, wherein the event page array is correlated to the received command with a same index array; 
 re-ordering the overlapping commands using time stamps from the event page; and 
 ignoring duplicate commands based on indexes of the overlapping commands being the same.