US11079641B2ActiveUtilityA1
Display panel and manufacturing method thereof
Assignee: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECH CO LTDPriority: Jan 30, 2019Filed: May 17, 2019Granted: Aug 3, 2021
Est. expiryJan 30, 2039(~12.5 yrs left)· nominal 20-yr term from priority
Inventors:Zesheng Chen
H10D 86/441H10D 86/60H10D 86/451G02F 1/136286G02F 1/136277G02F 1/13454H01L 27/124
39
PatentIndex Score
0
Cited by
8
References
13
Claims
Abstract
A display panel and a manufacturing method thereof are provided. The display panel includes a substrate having a semiconductor film layer structure which is provided with an active area, a plurality of data lines disposed on the active area of the transparent substrate, a plurality of scan lines disposed on the active area of the transparent substrate, wherein the scan lines are perpendicular to the data lines, and a plurality of leads electrically connected to the corresponding scan lines, and the leads parallel to the data lines.
Claims
exact text as granted — not AI-modifiedWhat is claimed is:
1. A display panel, comprising:
a substrate having a semiconductor film layer structure, wherein the semiconductor film layer structure is provided with a gate driver on array region, an active area, and an integrated circuit region, the gate driver on array region is opposite to the integrated circuit region, and the active area is located between the gate driver on array region and the integrated circuit region, wherein the semiconductor film layer structure comprises: a first metal layer, an interlayer insulation layer, a second metal layer, and a planarization layer, the interlayer insulation layer is disposed between the first metal layer and the second metal layer, the planarization layer is disposed on the second metal layer, and the planarization layer has a plurality of conductive holes;
a plurality of data lines disposed on the active area of the substrate, wherein the data lines are formed by a patterning process for the second metal layer;
a plurality of scan lines disposed on the active area of the substrate, wherein the scan lines are perpendicular to the data lines, and the scan lines are formed by a patterning process for the first metal layer; and
a lower transparent conductive layer disposed on the planarization layer, wherein the lower transparent conductive layer is formed into a plurality of leads by a patterning process for the lower transparent conductive layer, the leads are electrically connected to the corresponding scan lines through the conductive holes, and the leads are parallel to the data lines;
wherein one of the leads misaligns with one of the data lines.
2. The display panel according to claim 1 , wherein at least one of the leads is disposed between two adjacent data lines.
3. The display panel according to claim 1 , further comprising an insulation layer and an upper transparent conductive layer, wherein the insulation layer is disposed on the leads, and the upper transparent conductive layer is disposed on the insulation layer and is electrically connected to the data lines.
4. The display panel according to claim 3 , wherein the lower transparent conductive layer and the upper transparent conductive layer are made of a transparent conductive material.
5. A display panel, comprising:
a substrate having a semiconductor film layer structure, wherein the semiconductor film layer structure is provided with a gate driver on array region, an active area, and an integrated circuit region, the gate driver on array region is opposite to the integrated circuit region, and the active area is located between the gate driver on array region and the integrated circuit region, wherein the semiconductor film layer structure comprises: a gate insulation layer, a first metal layer, an interlayer insulation layer, a second metal layer, and a planarization layer;
a plurality of data lines disposed on the active area of the substrate, wherein the data lines are formed from the second metal layer disposed on the interlayer insulation layer;
a plurality of scan lines disposed on the active area of the substrate, wherein the scan lines are perpendicular to the data lines, and the scan lines are formed from the first metal layer disposed on the gate insulation layer; and
a plurality of leads electrically connected the corresponding scan lines with the gate driver on array region, and the leads are parallel to the data lines, wherein the leads are formed from a lower transparent conductive layer disposed on the planarization layer, and one of the leads misaligns with one of the data lines.
6. The display panel according to claim 5 , wherein at least one of the leads is disposed between two adjacent data lines.
7. The display panel according to claim 5 , further comprising an insulation layer and an upper transparent conductive layer, wherein the insulation layer is disposed on the leads, and the upper transparent conductive layer is disposed on the insulation layer and is electrically connected to the data lines.
8. The display panel according to claim 7 , wherein the leads and the upper transparent conductive layer are made of a transparent conductive material.
9. A display panel, comprising:
a substrate having a semiconductor film layer structure, wherein the semiconductor film layer structure is provided with an active area, wherein the semiconductor film layer structure comprises: a gate insulation layer, a first metal layer, an interlayer insulation layer, a second metal layer, and a planarization layer;
a plurality of data lines disposed on the active area of the substrate, wherein the data lines are formed from the second metal layer disposed on the interlayer insulation layer;
a plurality of scan lines disposed on the active area of the substrate, wherein the scan lines are perpendicular to the data lines, and the scan lines are formed from the first metal layer disposed on the gate insulation layer; and
a plurality of leads electrically connected to the corresponding scan lines, and the leads are parallel to the data lines, wherein the leads are formed from a lower transparent conductive layer disposed on the planarization layer, and one of the leads misaligns with one of the data lines.
10. The display panel according to claim 9 , wherein the semiconductor film layer structure comprises: a first metal layer, an interlayer insulation layer, a second metal layer, and a planarization layer, the interlayer insulation layer is disposed between the first metal layer and the second metal layer, the planarization layer is disposed on the second metal layer, and the planarization layer has a plurality of conductive holes.
11. The display panel according to claim 10 , wherein the scan lines are formed by a patterning process for the first metal layer, the data lines are formed by a patterning process for the second metal layer, and the leads are electrically connected to the corresponding scan lines through the conductive holes.
12. The display panel according to claim 11 , wherein the leads are made of a transparent conductive material.
13. The display panel according to claim 11 , wherein at least one of the leads is disposed between two adjacent data lines.Join the waitlist — get patent alerts
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