Encoding apparatus, decoding apparatus, encoding method, and decoding method

Abstract

An encoding apparatus includes: a circuit; and a memory. The circuit, using the memory: writes a first parameter that specifies an arrangement order for a plurality of parameters which includes a second parameter, into a header; writes a second parameter for a block into a bitstream according to the arrangement order wherein the second parameter, when positioned earlier in the arrangement order than later in the arrangement order, is written with less bits; and performs encoding operation for a block using the second parameter.

What is claimed is: 
     
       1. An encoding apparatus, comprising:
 a circuit; and 
 a memory, 
 wherein the circuit, using the memory:
 writes a first parameter that specifies an arrangement order for a plurality of parameters which includes a second parameter, into a header, the plurality of parameters including a motion vector predictor and an intra most probable mode, and the second parameter being a reference picture index; 
 writes the second parameter for a block into a bitstream according to the arrangement order, the second parameter being a parameter related to inter prediction; and 
 
 performs encoding operation for a block using the second parameter, 
 wherein when writing the second parameter into the bitstream according to the arrangement order, the second parameter is written with less bits when the second parameter is positioned earlier in the arrangement order than when the second parameter is positioned later in the arrangement order, and 
 wherein when writing the second parameter into the bitstream according to the arrangement order, the second parameter is binarized into less binary symbols when the second parameter is positioned earlier in the arrangement order than when the second parameter is positioned later in the arrangement order. 
 
     
     
       2. The encoding apparatus according to  claim 1 ,
 wherein, the circuit, using the memory:
 performs a first encoding of at least a portion of a picture using at least a prediction process and a transform process; 
 derives from the first encoding the arrangement order for the plurality of parameters which includes the second parameter; 
 writes the first parameter specifying the derived arrangement order into the header; and 
 performs a second encoding of the portion of the picture using the derived arrangement order wherein the second encoding does not include a prediction process, a transform process, and a quantization process and the second encoding includes writing a plurality of second parameters into a bitstream. 
 
 
     
     
       3. The encoding apparatus according to  claim 1 ,
 wherein the circuit, using the memory:
 writes a third parameter that identifies an arrangement order for a plurality of partitioning operations into a header; 
 writes a fourth parameter to identify a partitioning operation for a block into a bitstream; 
 performs an operation to partition a block based on the third parameter and the fourth parameter; and 
 encodes the partitioned block. 
 
 
     
     
       4. The encoding apparatus according to  claim 3 ,
 wherein the plurality of block partitioning operations includes at least one of an operation to split a block into four blocks, an operation to split a block horizontally into two blocks, and an operation to split a block vertically into two blocks, and 
 the second encoding includes writing a block partitioning operation into a bitstream using the derived arrangement order. 
 
     
     
       5. The encoding apparatus according to  claim 1 ,
 wherein the circuit, using the memory:
 performs a first encoding of at least a portion of a picture using at least a prediction process and a transform process; 
 derives from the first encoding an arrangement order for a plurality of block partitioning operations for the portion of the picture; 
 writes one or more parameters related to the derived arrangement order into a header; and 
 performs a second encoding of the portion of the picture using the derived arrangement order wherein the second encoding does not include a prediction process, a transform process, and a quantization process. 
 
 
     
     
       6. The encoding apparatus according to  claim 1 ,
 wherein the circuit, using the memory:
 writes one or more parameters related to a process to define a plurality of motion vector candidates into a header; 
 writes a motion vector candidate index for a block into a bitstream; 
 
 derives a motion vector for the block using at least the plurality of motion vector candidates and the motion vector candidate index; and
 encodes a block using a motion compensation process based on the derived motion vector. 
 
 
     
     
       7. The encoding apparatus according to  claim 1 ,
 wherein the circuit, using the memory:
 performs a first encoding of at least a portion of a picture using at least a prediction process; 
 derives from the first encoding a plurality of motion vector candidates for the portion of the picture; 
 writes one or more parameters related to the plurality of motion vector candidates into a header; and 
 performs a second encoding of the portion of the picture using the plurality of motion vector candidates wherein the second encoding does not include a prediction process, a transform process, and a quantization process. 
 
 
     
     
       8. The encoding apparatus according to  claim 7 ,
 wherein the second encoding includes writing a motion vector candidate index into a bitstream using the plurality of motion vector candidates. 
 
     
     
       9. The encoding apparatus according to  claim 7 ,
 wherein the one or more parameters is used for at least one of an operation to rearrange the order of the plurality of motion vector candidates, an operation to add or remove a motion vector candidate to/from the plurality of motion vector candidates, and an operation to select a plurality of motion vector candidates from a larger set of candidates. 
 
     
     
       10. The encoding apparatus according to  claim 1 ,
 wherein the circuit, using the memory:
 performs a first encoding of at least a portion of a picture wherein first encoding includes a plurality of decisions on use of a block parameter to control a coding tool to encode blocks; 
 judges from the first encoding if the plurality of decisions all resulted in a common decision of not using the block parameter to control the coding tool to encode the blocks; 
 writes a parameter indicating the judgment into a header; and 
 performs a second encoding of the portion of the picture based on the judgment wherein the second encoding does not include a prediction process, a transform process, and a quantization process, and the bitstream produced by the second encoding does not include block parameters to control the coding tool for each block. 
 
 
     
     
       11. The encoding apparatus according to  claim 10 ,
 wherein the coding tool is one of an affine motion vector prediction tool, an illumination compensation tool, a chrominance prediction tool using luminance samples, and a block sample prediction tool utilizing a search algorithm. 
 
     
     
       12. The encoding apparatus according to  claim 1 ,
 wherein the circuit, using the memory:
 performs a first encoding of at least a portion of a picture using a first set of initial entropy coding probabilities or contexts; 
 selects from the first encoding a second set of initial entropy coding probabilities or contexts wherein the second set is different from the first set; 
 writes a parameter indicating the selection into a header; and 
 performs a second encoding of the portion of the picture based on the selection wherein the second encoding does not include a prediction process, a transform process, and a quantization process. 
 
 
     
     
       13. The encoding apparatus according to  claim 1 ,
 wherein the circuit, using the memory:
 writes a fifth parameter that selects one out of a plurality of encoding operations controlled by a sixth parameter, into a header; 
 writes the sixth parameter for a block into a bitstream wherein the sixth parameter is used to control more than one encoding operation selectable by the fifth parameter; and 
 performs an encoding operation for a block selected based on the fifth parameter and controlled by the sixth parameter. 
 
 
     
     
       14. The encoding apparatus according to  claim 1 ,
 wherein the plurality of parameters include an inter prediction mode. 
 
     
     
       15. A decoding apparatus, comprising:
 a circuit; and 
 a memory, 
 wherein the circuit, using the memory:
 parses a first parameter that specifies an arrangement order for a plurality of parameters which includes a second parameter, from a header, the plurality of parameters including a motion vector predictor and an intra most probable mode, and the second parameter being a reference picture index; 
 parses the second parameter for a block from a bitstream according to the arrangement order, the second parameter being a parameter related to inter prediction; and 
 performs decoding operation for a block using the second parameter, 
 
 wherein when parsing the second parameter from the bitstream according to the arrangement order, the second parameter is written with less bits when the second parameter is positioned earlier in the arrangement order than when the second parameter is positioned later in the arrangement order, and 
 wherein when parsing the second parameter from the bitstream according to the arrangement order, the second parameter is converted using less binary symbols when the second parameter is positioned earlier in the arrangement order than when the second parameter is positioned later in the arrangement order. 
 
     
     
       16. The decoding apparatus according to  claim 15 ,
 wherein the circuit, using the memory:
 parses a third parameter that identifies an arrangement order for a plurality of block partitioning operations from a header; 
 parses a fourth parameter to identify a partitioning operation for a block from a bitstream; 
 parses an operation to partition a block based on the third parameter and the fourth parameter; and 
 decodes the partitioned block. 
 
 
     
     
       17. The decoding apparatus according to  claim 16 ,
 wherein the plurality of block partitioning operations includes at least one of an operation to split a block into four blocks, an operation to split a block horizontally into two blocks, and an operation to split a block vertically into two blocks, and 
 the second encoding includes writing a block partitioning operation into a bitstream using the derived arrangement order. 
 
     
     
       18. The decoding apparatus according to  claim 15 ,
 wherein the circuit, using the memory:
 parses one or more parameters related to the process to define plurality of motion vector candidates from a header; 
 parses a motion vector candidate index for a block from a bitstream; 
 derives a motion vector for the block using at least the plurality of motion vector candidates and the motion vector candidate index; and 
 decodes a block using a motion compensation process based on the derived motion vector. 
 
 
     
     
       19. The decoding apparatus according to  claim 18 ,
 wherein the one or more parameters is used for at least one of an operation to rearrange the order of the plurality of motion vector candidates, an operation to add or remove a motion vector candidate to/from the plurality of motion vector candidates, and an operation to select a plurality of motion vector candidates from a larger set of candidates. 
 
     
     
       20. The decoding apparatus according to  claim 15 ,
 wherein the circuit, using the memory:
 parses a fifth parameter that selects one out of a plurality of decoding operations controlled by a sixth parameter, from a header; 
 parses the sixth parameter for a block from a bitstream wherein the sixth parameter is used to control more than one decoding operation selectable by the fifth parameter; and 
 performs a decoding operation for a block selected based on the fifth parameter and controlled by the sixth parameter. 
 
 
     
     
       21. The decoding apparatus according to  claim 15 ,
 wherein the plurality of parameters include an inter prediction mode. 
 
     
     
       22. An encoding method, comprising:
 writing a first parameter that specifies an arrangement order for a plurality of parameters which includes a second parameter, into a header, the plurality of parameters including a motion vector predictor and an intra most probable mode, and the second parameter being a reference picture index; 
 writing the second parameter for a block into a bitstream according to the arrangement order, the second parameter being a parameter related to inter prediction; and 
 performing encoding operation for a block using the second parameter, 
 wherein when writing the second parameter into the bitstream according to the arrangement order, the second parameter is written with less bits when the second parameter is positioned earlier in the arrangement order than when the second parameter is positioned later in the arrangement order, and 
 wherein when writing the second parameter into the bitstream according to the arrangement order, the second parameter is binarized into less binary symbols when the second parameter is positioned earlier in the arrangement order than when the second parameter is positioned later in the arrangement order. 
 
     
     
       23. A decoding method, comprising:
 parsing a first parameter that specifies an arrangement order for a plurality of parameters which includes a second parameter, from a header, the plurality of parameters including a motion vector predictor and an intra most probable mode, and the second parameter being a reference picture index; 
 parsing the second parameter for a block from a bitstream according to the arrangement order, the second parameter being a parameter related to inter prediction; and 
 performing decoding operation for a block using the second parameter, 
 wherein when parsing the second parameter from the bitstream according to the arrangement order, the second parameter is written with less bits when the second parameter is positioned earlier in the arrangement order than when the second parameter is positioned later in the arrangement order, and 
 wherein when parsing the second parameter from the bitstream according to the arrangement order, the second parameter is converted using less binary symbols when the second parameter is positioned earlier in the arrangement order than when the second parameter is positioned later in the arrangement order.