Radio communication apparatus and radio communication method

Abstract

Provided is a radio communication device which can make Acknowledgement (ACK) reception quality and Negative Acknowledgement (NACK) reception quality to be equal to each other. The device includes: a scrambling unit ( 214 ) which multiplies a response signal after modulated, by a scrambling code “1” or “e −j(π/2) ” so as to rotate a constellation for each of response signals on a cyclic shift axis; a spread unit ( 215 ) which performs a primary spread of the response signal by using a Zero Auto Correlation (ZAC) sequence set by a control unit ( 209 ); and a spread unit ( 218 ) which performs a secondary spread of the response signal after subjected to the primary spread, by using a block-wise spread code sequence set by the control unit ( 209 ).

The invention claimed is: 
     
       1. An integrated circuit to control a process, the process comprising:
 multiplying a symbol representing an Acknowledgment (ACK) or Negative Acknowledgement (NACK) with a sequence defined by one of a plurality of cyclic shift values and also multiplying the symbol by e j(π/2)  when an index of a resource to which a physical uplink control channel is mapped is odd, said one of the plurality of cyclic shift values being determined from the index; and 
 transmitting the multiplied symbol on the physical uplink control channel. 
 
     
     
       2. The integrated circuit according to  claim 1 , comprising:
 circuitry which, in operation, controls the process; 
 at least one input coupled to the circuitry, wherein the at least one input, in operation, inputs data; and 
 at least one output coupled to the circuity, wherein the at least one output, in operation, outputs data. 
 
     
     
       3. The integrated circuit according to  claim 1 , wherein the multiplying includes multiplying the symbol by e j(π/2)  depending on said one of the plurality of cyclic shift values. 
     
     
       4. The integrated circuit according to  claim 1 , wherein the multiplying includes multiplying the symbol by e j(π/2)  depending on the sequence defined by said one of the plurality of cyclic shift values. 
     
     
       5. The integrated circuit according to  claim 1 , wherein the multiplying includes multiplying the symbol by e j(π/2)  when the resource is one of two resources and multiplies the symbol by 1 when the resource is the other of said two resources, said two resources being respectively associated with two cyclic shift values of the plurality of cyclic shift values, and a difference between said two cyclic shift values being a given value. 
     
     
       6. The integrated circuit according to  claim 1 , wherein the process comprises multiplying the symbol with one of a plurality of orthogonal sequences, said one of the plurality of orthogonal sequences being determined from the index. 
     
     
       7. The integrated circuit according to  claim 6 , wherein the multiplying includes multiplying the symbol by e j(π/2)  when the resource is one of two resources and multiplies the symbol by 1 when the resource is the other of said two resources, said two resources being associated with one of the plurality of orthogonal sequences and being respectively associated with two cyclic shift values of the plurality of cyclic shift values, and a difference between said two cyclic shift values being a given value. 
     
     
       8. The integrated circuit according to  claim 1 , wherein the process comprises not multiplying the symbol by e j(π/2)  when the index is even. 
     
     
       9. The integrated circuit according to  claim 8 , wherein the symbol is scrambled by multiplying the symbol by e j(π/2)  when the index is odd and not multiplying the symbol by e j(π/2)  when the index is even. 
     
     
       10. An integrated circuit comprising circuitry, which, in operation:
 multiplies a symbol representing an Acknowledgment (ACK) or Negative Acknowledgement (NACK) with a sequence defined by one of a plurality of cyclic shift values and also multiplies the symbol by e j(π/2)  when an index of a resource to which a physical uplink control channel is mapped is odd, said one of the plurality of cyclic shift values being determined from the index; and 
 control transmission of the multiplied symbol on the physical uplink control channel. 
 
     
     
       11. The integrated circuit according to  claim 10 , comprising:
 at least one input coupled to the circuitry, wherein the at least one input, in operation, inputs data; and 
 at least one output coupled to the circuity, wherein the at least one output, in operation, outputs data. 
 
     
     
       12. The integrated circuit according to  claim 10 , wherein the circuitry, in operation, multiplies the symbol by e j(π/2)  depending on said one of the plurality of cyclic shift values. 
     
     
       13. The integrated circuit according to  claim 10 , wherein the circuitry, in operation, multiplies the symbol by e j(π/2)  depending on the sequence defined by said one of the plurality of cyclic shift values. 
     
     
       14. The integrated circuit according to  claim 10 , wherein the circuitry, in operation, multiplies the symbol by e j(π/2)  when the resource is one of two resources and multiplies the symbol by 1 when the resource is the other of said two resources, said two resources being respectively associated with two cyclic shift values of the plurality of cyclic shift values, and a difference between said two cyclic shift values being a given value. 
     
     
       15. The integrated circuit according to  claim 10 , wherein the circuitry, in operation, multiplies the symbol with one of a plurality of orthogonal sequences, said one of the plurality of orthogonal sequences being determined from the index. 
     
     
       16. The integrated circuit according to  claim 15 , wherein the circuitry, in operation, multiplies the symbol by e j(π/2)  when the resource is one of two resources and multiplies the symbol by 1 when the resource is the other of said two resources, said two resources being associated with one of the plurality of orthogonal sequences and being respectively associated with two cyclic shift values of the plurality of cyclic shift values, and a difference between said two cyclic shift values being a given value. 
     
     
       17. The integrated circuit according to  claim 10 , wherein the circuitry, in operation, does not multiply the symbol by e j(π/2)  when the index is even. 
     
     
       18. The integrated circuit according to  claim 17 , wherein the symbol is scrambled by multiplying the symbol by e j(π/2)  when the index is odd and not multiplying the symbol by e j(π/2)  when the index is even.