Interconnect structures, packaged semiconductor devices, and methods of packaging semiconductor devices

Abstract

Interconnect structures, packaged semiconductor devices, and methods of packaging semiconductor devices are disclosed. In some embodiments, an interconnect structure includes dielectric layers, a conductive layer disposed in the dielectric layers, and a via layer disposed in the dielectric layers proximate the conductive layer. An underball metallization (UBM) layer is disposed in the dielectric layers proximate the via layer. A first connector coupling region is disposed in the via layer and the UBM layer. A via layer portion of the first connector coupling region is coupled to a first contact pad in the conductive layer. A second connector coupling region is disposed in the UBM layer. The second connector coupling region is coupled to a conductive segment in the UBM layer and the via layer. The second connector coupling region is coupled to a second contact pad in the conductive layer by the conductive segment.

What is claimed is: 
     
       1. A method of forming a semiconductor structure, the method comprising:
 encapsulating an integrated circuit die and a plurality of through-vias with a molding material; 
 forming an interconnect structure on the integrated circuit die, the plurality of through-vias, and the molding material, comprising:
 depositing a conductive layer having a first contact pad and a second contact pad; 
 depositing a first dielectric layer on the conductive layer; 
 forming a ground-up underbump metallization (UBM) pad disposed on the first dielectric layer in a first region of the interconnect structure, the first region of the interconnect structure being subject to a first amount of stress during operation, a first portion of the ground-up UBM pad extending through the first dielectric layer to contact the first contact pad in the conductive layer, the first portion of the ground-up UBM pad having a recessed top surface; and 
 forming a post-passivation interconnect (PPI) on the first dielectric layer, the PPI being a single continuous conductive material in a second region of the interconnect structure, the second region of the interconnect structure being subject to a second amount of stress during operation, the second amount of stress less than the first amount of stress, the PPI comprising a PPI pad and a conductive segment, the conductive segment extending through the first dielectric layer to contact the second contact pad in the conductive layer, the PPI pad having a flat top surface; 
 
 coupling a first connector to the ground-up UBM pad, the first connector contacting sidewalls and the recessed top surface of the ground-up UBM pad; 
 coupling a second connector to the PPI pad, the second connector physically contacting the flat top surface of the PPI pad; and 
 after coupling the second connector to the PPI pad, depositing a second dielectric layer on the interconnect structure, the second dielectric layer covering a portion of a spherical surface of the first connector, the second dielectric layer being directly adjacent to at least a first portion of a lower half of a spherical surface of the second connector, at least a second portion of the lower half of the spherical surface of the second connector being directly adjacent to an ambient, the second dielectric layer covering a sidewall of the PPI pad. 
 
     
     
       2. The method of  claim 1 , wherein the conductive layer is disposed on conductive material layers. 
     
     
       3. The method of  claim 2 , wherein the conductive material layers comprise a plurality of conductive lines and vias. 
     
     
       4. The method of  claim 3 , wherein at least some of the plurality of conductive lines and vias are coupled to respective through-vias of the plurality of through-vias. 
     
     
       5. The method of  claim 3 , further comprising depositing a passivation layer over the integrated circuit die. 
     
     
       6. The method of  claim 5  further comprising forming an opening through the passivation layer. 
     
     
       7. The method of  claim 6  further comprising electrically connecting the integrated circuit die to at least some through-vias of the plurality of through-vias through the opening through the passivation layer. 
     
     
       8. A method of forming a semiconductor device, the method comprising:
 encapsulating a plurality of dies and a plurality of through-vias by depositing a molding material over the plurality of dies and the plurality of through-vias; 
 forming an interconnect on the plurality of dies, the plurality of through-vias, and the molding material, comprising:
 depositing a conductive layer having a plurality of first contact pads and a plurality of second contact pads; 
 depositing a first dielectric layer on the conductive layer; 
 forming a plurality of ground-up underbump metallization (UBM) pads directly on the first dielectric layer in respective first regions of the interconnect, a plurality of respective lower surfaces of the plurality of ground-up UBM pads physically contacting an upper surface of the first dielectric layer, the respective first regions of the interconnect having a respective first amount of reliability risk over a threshold amount of reliability risk, a plurality of respective first portions of the plurality of ground-up UBM pads extending through the first dielectric layer to contact respective first contact pads of the plurality of first contact pads in the conductive layer, each of the respective first portions of the plurality of ground-up UBM pads having a respective recessed top surface; and 
 forming a plurality of post-passivation interconnects (PPIs) directly on the first dielectric layer, each of the plurality of PPIs being a single continuous conductive material in respective second regions of the interconnect, the respective second regions of the interconnect having a second amount of reliability risk under the threshold amount of reliability risk, each of the plurality of PPIs comprising a respective PPI pad and a respective conductive segment, the respective conductive segments extending through the first dielectric layer to contact respective second contact pads of the plurality of second contact pads in the conductive layer, each respective PPI pad having a flat top surface, a respective lower surface of each respective PPI pad physically contacting the upper surface of the first dielectric layer; 
 
 coupling a plurality of first connectors to respective ground-up UBM pads, each of the plurality of first connectors contacting respective sidewalls and respective recessed top surfaces of the respective ground-up UBM pads; 
 coupling a plurality of second connectors to respective PPI pads, each of the plurality of second connectors physically contacting respective flat top surface of respective PPI pads; and 
 depositing a second dielectric layer on the interconnect, the second dielectric layer covering respective portions of respective spherical surfaces of first connectors of the plurality of first connectors, the second dielectric layer covering at least respective first portions of respective lower halves of respective spherical surfaces of second connectors of the plurality of second connectors, respective second portions of the respective lower halves of the respective spherical surfaces of the second connectors being directly adjacent to an ambient, the second dielectric layer covering respective sidewalls of respective PPI pads of the plurality of PPIs. 
 
     
     
       9. The method of  claim 8  further comprising forming an array comprising the plurality of first connectors and the plurality of second connectors. 
     
     
       10. The method of  claim 9 , wherein a neutral point comprises the center of the array, wherein the respective first regions comprise a first distance to a neutral point (DNP), wherein the respective second regions comprise a second DNP, and wherein the first DNP is greater than the second DNP. 
     
     
       11. The method of  claim 9 , wherein the array is a ball grid array. 
     
     
       12. The method of  claim 8 , wherein the respective first regions comprise a corner region of the interconnect. 
     
     
       13. The method of  claim 8 , wherein the respective first regions comprise an edge region of the semiconductor device. 
     
     
       14. A method of forming a semiconductor device, the method comprising:
 determining an initial interconnect structure design for the semiconductor device, the initial interconnect structure design comprising a plurality of connector coupling regions, each connector coupling region of the plurality of connector coupling regions comprising a respective post-passivation interconnect (PPI) pad; 
 determining a respective amount of reliability risk for each connector coupling region of the plurality of connector coupling regions; 
 determining a threshold amount of reliability risk; 
 altering the initial interconnect structure design by replacing a first PPI pad in a first connector coupling region of the plurality of connector coupling regions with a first ground-up underball metallization (UBM) pad, the first connector coupling region having a first amount of reliability risk greater than the threshold amount of reliability risk; 
 forming a first interconnect structure comprising the altered interconnect structure design, the forming the first interconnect structure comprising:
 depositing a conductive layer having a first contact pad and a second contact pad; 
 depositing a first dielectric layer on the conductive layer; 
 forming the first ground-up UBM pad directly on the first dielectric layer in the first connector coupling region, a lower surface of the first ground-up UBM pad physically contacting an upper surface of the first dielectric layer, a first portion of the first ground-up UBM pad extending through the first dielectric layer to contact the first contact pad in the conductive layer, the first portion of the first ground-up UBM pad having a recessed top surface; and 
 forming a post-passivation interconnect (PPI) directly on the first dielectric layer in a second connector coupling region of the plurality of connector coupling regions, the second connector coupling region having a second amount of reliability risk less than the threshold amount of reliability risk, the PPI comprising a second PPI pad and a conductive segment, the conductive segment extending through the first dielectric layer to contact the second contact pad in the conductive layer, a lower surface of the second PPI pad physically contacting the upper surface of the first dielectric layer; 
 
 coupling a first connector to the first ground-up UBM pad and coupling a second connector to the second PPI pad; and 
 depositing a second dielectric layer on the first interconnect structure, the second dielectric layer consisting essentially of silicon nitride, silicon dioxide, or silicon oxynitride, the second dielectric layer covering a portion of a spherical surface of the first connector, the second dielectric layer covering at least a first portion of a lower half of a spherical surface of the second connector, at least a second portion of a lower half of a spherical surface of the second connector being directly adjacent to an ambient, the second dielectric layer covering a sidewall of the second PPI pad. 
 
     
     
       15. The method of  claim 14 , wherein forming the first interconnect structure further c comprises forming the first interconnect structure over an integrated circuit die and a molding material, the molding material encapsulating the integrated circuit die. 
     
     
       16. The method of  claim 15 , wherein the molding material further encapsulates a plurality of through-vias. 
     
     
       17. The method of  claim 16  further comprising forming a second interconnect structure over the integrated circuit die, the plurality of through-vias, and the molding material. 
     
     
       18. The method of  claim 14 , wherein the PPI is a single continuous conductive material. 
     
     
       19. The method of  claim 15 , wherein the integrated circuit die comprises a DRAM device. 
     
     
       20. The method of  claim 17  further comprising coupling a plurality of third connectors to the second interconnect structure.