Floating gate prevention and capacitance reduction in semiconductor devices

Abstract

A method for fabricating a semiconductor structure includes forming a plurality of vertical fins on a semiconductor substrate. The method further includes depositing a first dielectric layer in a shallow trench isolation region on the semiconductor substrate. The method further includes forming a plurality of dummy gate structures over each of the vertical fins. The method further includes depositing a hardmask on the dummy gate. The method further includes depositing a spacer layer on the exterior surfaces of the first dielectric layer, the dummy gate structures, the hardmask and the fins. The method further includes depositing a second dielectric layer on a portion of the spacer layer. The method further includes recessing spacer layer to expose a portion of the hardmask and the plurality of fins. The method further includes forming a source/drain region on the exposed portion of the plurality of fins.

What is claimed is: 
     
       1. A method for fabricating a semiconductor structure comprising:
 forming a plurality of vertical fins on a semiconductor substrate; 
 depositing a first dielectric layer in a shallow trench isolation region on the semiconductor substrate and between each of the vertical fins to expose a top portion of the vertical fins; 
 forming a plurality of dummy gate structures over a portion of each of the vertical fins; 
 depositing a hardmask on each of the dummy gate structures; 
 depositing a spacer layer on the exterior surfaces of the first dielectric layer, the dummy gate structures, the hardmask and the vertical fins; 
 depositing a second dielectric layer on a portion of the spacer layer; 
 recessing the spacer layer to below a top surface of the hardmask and a top surface of each of the vertical fins thereby exposing a portion of sidewalls of the hardmask and the vertical fins; and 
 forming a source/drain region on the exposed portion of the vertical fins. 
 
     
     
       2. The method of  claim 1 , wherein the semiconductor substrate and each of the vertical fins comprise silicon. 
     
     
       3. The method of  claim 1 , wherein the second dielectric layer is recessed to below a top surface of the spacer layer. 
     
     
       4. The method of  claim 1 , further comprising:
 depositing a contact etching stop layer on the source drain region, a top surface of the second dielectric layer and on the spacer layer disposed between adjacent dummy gate structures; and 
 depositing an interlevel dielectric layer on the contact etching stop layer. 
 
     
     
       5. The method of  claim 4 , further comprising:
 replacing the dummy gate structures with replacement metal gates; and 
 depositing a self-aligned contact cap layer on a top surface of replacement metal gates. 
 
     
     
       6. The method of  claim 5 , wherein the replacement metal gates comprise a metal gate and a gate dielectric. 
     
     
       7. The method of  claim 6 , wherein the gate dielectric comprises a high-k dielectric material. 
     
     
       8. The method of  claim 5 , further comprising:
 forming a source/drain contact trench by etching a portion of the interlevel dielectric layer, wherein the source/drain contact trench exposes at least a portion of the source/drain region; and 
 depositing a first conductive metal in the source/drain contact trench. 
 
     
     
       9. The method of  claim 8 , wherein the first conductive metal comprises copper. 
     
     
       10. The method of  claim 8 , wherein the source/drain contact trench is separated from the shallow trench isolation region by at least the spacer layer. 
     
     
       11. The method of  claim 1 , wherein the plurality of vertical fins comprise a first set of vertical fins for forming a first field effect transistor device and a second set of vertical fins for forming a second field effect transistor device, wherein the first set of vertical fins are separated from the second set of vertical fins by the second dielectric layer disposed on the spacer layer. 
     
     
       12. The method of  claim 11 , wherein the first field effect transistor is a P-type field effect transistor and the second field effect transistor is a N-type field effect transistor. 
     
     
       13. The method of  claim 1 , wherein the first dielectric layer comprises SiO 2 . 
     
     
       14. The method of  claim 1 , wherein the second dielectric layer comprises silicon carbide. 
     
     
       15. The method of  claim 4 , wherein the interlevel dielectric layer on the contact etching stop layer disposed between one of the adjacent dummy gate structures is replaced with a second conductive metal. 
     
     
       16. The method of  claim 15 , wherein the second conductive metal is the same as the first conductive metal. 
     
     
       17. The method of  claim 4 , wherein the contact etching stop layer comprises one or more of silicon nitride, silicon carbon nitride, carbon nitride, silicon oxynitride, and silicon carbon oxide. 
     
     
       18. A semiconductor structure comprising:
 a semiconductor substrate having a plurality of vertical fins; 
 a first dielectric layer disposed in a shallow trench isolation region on a top surface of the semiconductor substrate and between each of the vertical fins to expose a top portion of the vertical fins; 
 a plurality of dummy gate structures disposed over a portion of each of the vertical fins; 
 a hardmask disposed on the dummy gate structures; 
 a recessed spacer layer disposed on the exterior surfaces of the first dielectric layer, the dummy gate structures, the hardmask and the vertical fins, the recessed spacer layer configured to expose a portion of sidewalls of the hardmask and the vertical fins; 
 a second dielectric layer disposed on a portion of the recessed spacer layer; and 
 a source/drain region disposed on the exposed portion of the plurality of the vertical fins. 
 
     
     
       19. The semiconductor structure of  claim 18 , further comprising:
 a contact etching stop layer disposed on the source drain region, a top surface of the second dielectric layer and on the recessed spacer layer disposed between adjacent dummy gate structures; and 
 an interlevel dielectric layer disposed on the contact etching stop layer. 
 
     
     
       20. The semiconductor structure of  claim 18 , wherein the semiconductor substrate and each of the vertical fins comprise silicon.