Background offset drift calibration circuit and method for comparator

Abstract

A background offset drift calibration circuit and method for comparator are proposed. The background calibration circuit and method are designed based on the approximate linear characteristic of the offset drift of a comparator caused by the variation of temperature and power supply. The calibration circuit for the comparators obtains the offset drift characteristic of each comparator by performing twice foreground calibration and selects the comparator with the largest drift as the reference comparator and other comparators as working comparators. The reference comparator is configured to track the offset drift and trigger the background calibration circuit of other working comparators. The working comparators compensate for the offset drift caused by the temperature or the power supply in the background by linear interpolation based on the offset drift characteristic of each comparator.

The invention claimed is: 
     
       1. A background offset drift calibration circuit for comparators, comprising a plurality of comparators, wherein the plurality of comparators comprises a reference comparator and a plurality of working comparators; wherein,
 the reference comparator is configured to detect an offset voltage drift caused by a temperature and a power supply, and 
 the plurality of working comparators are configured to perform a background calibration on the offset voltage drift caused by the temperature and the power supply based on a tracking result of the reference comparator; wherein 
 the reference comparator is a comparator with the largest offset voltage drift among the plurality of comparators; the reference comparator tracks the offset voltage drift and triggers the plurality of working comparators to compensate the offset voltage drift caused by the temperature and the power supply by linear interpolation in a background; 
 wherein, the offset voltage drift of each of the plurality of the comparators caused by variations of the temperature and the power supply indicates predetermined linearity characteristics for the linear interpolation. 
 
     
     
       2. The background offset drift calibration circuit for the comparators according to  claim 1 , wherein, a circuit of the reference comparator is identical to a circuit of the plurality of working comparators, the reference comparator works in a tracking mode, and the plurality of working comparators work in a comparing mode. 
     
     
       3. The background offset drift calibration circuit for the comparators according to  claim 1 , comprising an analog signal input port, a calibration switch circuit, a preamplifier circuit, a reset switch, a dynamic comparator circuit, a calibration control logic circuit, a bidirectional counter circuit, a digital-to-analog converter circuit, an offset calibration voltage input circuit and an output port; wherein
 the calibration switch circuit is connected to a Vin+ terminal and a Vin− terminal of the analog signal input port; the analog signal input port is connected to the preamplifier circuit and the analog signal input port acts as an input of the preamplifier circuit; an input terminal of the preamplifier circuit is connected to a common-mode voltage input terminal Vcm; an output of the preamplifier circuit is connected to an input of the dynamic comparator circuit; a positive input terminal and a negative input terminal of the dynamic comparator circuit are connected to the reset switch to reset the input of the dynamic comparator; an output of the dynamic comparator circuit is connected to a Vout+ terminal and a Vout− terminal of the output port and the output of the dynamic comparator circuit serves as an input of the calibration control logic circuit; a first output of the calibration control logic circuit is configured as an input of the bidirectional counter circuit, and a second output of the calibration control logic circuit is connected to a control signal port of the plurality of working comparators; an output clock signal of the calibration control logic circuit serves as a working clock input of the bidirectional counter circuit and a working clock input of the digital-to-analog converter circuit; an output of the bidirectional counter circuit is connected to an input of the digital-to-analog converter circuit, and the digital-to-analog converter circuit converts a count value of the bidirectional counter circuit into an analog voltage corresponding the count value; and an output of the digital-to-analog converter circuit is connected to the offset calibration voltage input circuit and the output of the digital-to-analog converter circuit outputs an offset calibration voltage to the preamplifier circuit to calibrate an offset. 
 
     
     
       4. The background offset drift calibration circuit for the comparators according to  claim 3 , wherein, the calibration control logic circuit comprises a first calibration value register, a twice-calibrating difference value register, an offset voltage drift value register, a drift calibration trigger circuit, a linear interpolation calculation circuit and a drift calibration value register; wherein
 the first calibration value register is connected to the output of the bidirectional counter circuit to store a bidirectional counter value of a first foreground calibration of each of the plurality of comparators; the twice-calibrating difference value register is connected to the output of the bidirectional counter circuit to store a difference value between the first foreground calibration and a second foreground calibration of the comparator from the bidirectional counter; the twice-calibrating difference value register is further connected to the linear interpolation calculation circuit of the plurality of working comparators to calculate a drift calibration value; the offset voltage drift value register is connected to the output of the bidirectional counter circuit to store a difference value between a first calibration value and a current value of the bidirectional counter, wherein the difference value between the first calibration value and the current value of the bidirectional counter represents the offset voltage drift caused by the temperature and the power supply detected by the reference comparator; the drift calibration trigger circuit is connected to the linear interpolation calculation circuit of the plurality of working comparators to trigger the linear interpolation calculation circuit of the plurality of working comparators and the linear interpolation calculation circuit is configured to calculate the drift calibration value according to an approximate linear drift characteristic curve of each of the plurality of working comparators; the linear interpolation calculation circuit of the plurality of working comparators is connected to the drift calibration value register to store the generated drift calibration value in the drift calibration value register; the drift calibration value register is connected to the digital-to-analog converter circuit to output the offset calibration voltage to Cal+/Cal− terminal of an offset calibration voltage input port of the preamplifier circuit. 
 
     
     
       5. A background offset drift calibration method for comparators, comprising the following steps:
 (1) powering on to restart the comparators, wherein the comparators enter an initial state; 
 (2) performing a first foreground offset calibration on the comparators to calibrate an offset voltage introduced by a manufacturing process, and storing a calibration value of the comparators in a first calibration value register, respectively; 
 (3) according to an application scenario, loading an offset drift calibration trigger value to a drift calibration trigger circuit to trigger a second foreground offset calibration, wherein the offset drift calibration trigger value can be set to 1 by default; 
 (4) choosing a comparator among the comparators to track an offset drift, and comparing a value of an offset voltage drift value register with the offset drift calibration trigger value of the drift calibration trigger circuit, wherein when the value of the offset voltage drift value register is equal to the offset drift calibration trigger value, the second foreground offset calibration is triggered; 
 (5) performing the second foreground offset calibration on the comparators to obtain a twice-calibrating difference value between the second foreground offset calibration and the first foreground offset calibration, and storing the twice-calibrating difference value in a twice-calibrating difference value register; 
 (6) among all the comparators, choosing a comparator with a largest twice-calibrating difference value as a reference comparator to track the offset drift and trigger a background calibration of working comparators; wherein the working comparators is the comparators excluding the reference comparator; 
 (7) tracking the offset drift in real time by the reference comparator working in a tracking mode; 
 (8) allowing the working comparators to function in a normal comparing operation mode; 
 (9) detecting whether the offset drift exceeds one calibration step by the reference comparator, wherein when the reference comparator detects that the offset drift exceeds one calibration step, the drift calibration trigger circuit in the reference comparator triggers an offset drift control signal to the working comparators; 
 (10) receiving the drift trigger control signal from the reference comparator by the working comparators, and starting to perform an offset drift calibration operation; 
 (11) calculating a drift calibration value through a linear interpolation calculation circuit in a calibration control logic circuit of the working comparators and storing the drift calibration value in a drift calibration value register; 
 (12) performing a background offset drift calibration, converting the value in the drift calibration value register into an offset drift calibration voltage through a digital-to-analog converter circuit, and outputting the offset drift calibration voltage to Cal+/Cal− terminal of an offset calibration voltage input port of a preamplifier circuit of the working comparators to calibrate the offset drift of the working comparators; wherein, when the background offset drift calibration is performed, the working comparators still function in a normal operation mode continuously; 
 (13) waiting for a completion signal of the background offset drift calibration by the working comparators; when the completion signal of the background offset drift calibration is acknowledged, the working comparator resumes normal function in a comparing operation mode, when the completion signal of the background offset drift calibration is not acknowledged, the working comparator continues to wait for the completion signal of the background offset drift calibration; and 
 (14) waiting for an offset drift calibration completion signal from all the working comparators by the reference comparator; wherein, when the offset drift calibration completion signal of all the working comparators is acknowledged, the reference comparator resumes the tracking mode and proceeds a new round of tracking the offset drift in real time, when the offset drift calibration completion signal of all the working comparators is not acknowledged, the reference comparator continues to wait for the offset drift calibration completion signal.