Spatial light modulator with embedded pattern generation

Abstract

A word data loading circuit for a spatial light modulator includes a shadow load register (SLR), a load controller, and a word pattern generation (WPG) circuit. The SLR loads a first word of a pseudorandom image pattern. The load controller parallel shifts the first word to a memory cell array. The WPG circuit generates a next word and controls the SLR to change the first word to the next word. The load controller parallel shifts the next word to the array. The WPG circuit generates an additional word and controls the SLR to change the next word to the additional word. The load controller parallel shifts the additional word to the array. The WPG circuit, SLR, and load controller generate and parallel shift further additional words to the array until the pseudorandom image pattern is loaded in the array.

The following is claimed: 
     
       1. A data loading circuit for a digital micromirror device (DMD), the DMD having a mirror element array coupled to a memory cell array, and the data loading circuit comprising:
 a shadow load register configured to store a current word of a current portion of a pseudorandom pattern of pixels, the pseudorandom pattern being formed by a series of words; 
 a load controller coupled to the shadow load register and adapted to be coupled the memory cell array, the load controller configured to parallel shift the current word from the shadow load register into a current row or column of the memory cell array and, after the parallel shift, designate a next row or column of the memory cell array as the current row or column; 
 a word pattern generation circuit coupled to the shadow load register, the word pattern generation circuit configured to: generate a next word of a next portion of the pseudorandom pattern based on the current word; and cause the shadow load register to store the next word as the current word; 
 a serial data receiver configured to receive a seed word from a system controller; and 
 a word shift register coupled to the serial data receiver; 
 in which the word pattern generation circuit, the shadow load register, and the load controller are configured to respectively generate, store and parallel shift the series of words into the memory cell array until the pseudorandom pattern is fully shifted into the memory cell array for causing the mirror element array to reflect the pseudorandom pattern of pixels from a scene; 
 the serial data receiver is configured to parallel shift portions of the seed word into the word shift register until the seed word is fully shifted in the word shift register; and 
 the word shift register is configured to parallel shift the seed word into the shadow load register. 
 
     
     
       2. The data loading circuit of  claim 1 , further comprising:
 a pattern data storage device coupled to the word pattern generation circuit; 
 in which the word pattern generation circuit is configured to: identify the seed word in the pattern data storage device; and parallel shift the seed word from the pattern data storage device into the shadow load register. 
 
     
     
       3. A data loading circuit for a digital micromirror device (DMD), the DMD having a mirror element array coupled to a memory cell array, and the data loading circuit comprising:
 a shadow load register configured to store a current word of a current portion of a pseudorandom pattern of pixels, the pseudorandom pattern being formed by a series of words; 
 a load controller coupled to the shadow load register and adapted to be coupled the memory cell array, the load controller configured to parallel shift the current word from the shadow load register into a current row or column of the memory cell array and, after the parallel shift, designate a next row or column of the memory cell array as the current row or column; and 
 a word pattern generation circuit coupled to the shadow load register, the word pattern generation circuit configured to: generate a next word of a next portion of the pseudorandom pattern based on the current word; and cause the shadow load register to store the next word as the current word; 
 in which the word pattern generation circuit, the shadow load register, and the load controller are configured to respectively generate, store and parallel shift the series of words into the memory cell array until the pseudorandom pattern is fully shifted into the memory cell array for causing the mirror element array to reflect the pseudorandom pattern of pixels from a scene; and 
 the word pattern generation circuit is configured to generate the next word using a Toeplitz shift mode in accordance with a Toeplitz matrix. 
 
     
     
       4. A data loading circuit for a digital micromirror device (DMD), the DMD having a mirror element array coupled to a memory cell array, and the data loading circuit comprising:
 a shadow load register configured to store a current word of a current portion of a pseudorandom pattern of pixels, the pseudorandom pattern being formed by a series of words; 
 a load controller coupled to the shadow load register and adapted to be coupled the memory cell array, the load controller configured to parallel shift the current word from the shadow load register into a current row or column of the memory cell array and, after the parallel shift, designate a next row or column of the memory cell array as the current row or column; and 
 a word pattern generation circuit coupled to the shadow load register, the word pattern generation circuit configured to: generate a next word of a next portion of the pseudorandom pattern based on the current word; and cause the shadow load register to store the next word as the current word; 
 in which the word pattern generation circuit, the shadow load register, and the load controller are configured to respectively generate, store and parallel shift the series of words into the memory cell array until the pseudorandom pattern is fully shifted into the memory cell array for causing the mirror element array to reflect the pseudorandom pattern of pixels from a scene; 
 the shadow load register is configured to store n bits; and 
 the word pattern generation circuit is configured to generate the next word by serially shifting contents of first through n- 1  bits of the shadow load register to second through n bit positions and generating content for a first bit position in the shadow load register using a linear feedback shift register (LFSR) that taps select bits of the shadow load register as inputs to an exclusive-OR logic circuit and feeds back an output of the exclusive-OR logic circuit to the first bit position of the shadow load register. 
 
     
     
       5. The data loading circuit of  claim 4 , wherein the word pattern generation circuit is configured to generate the next word for the shadow load register using a circulant shift mode in accordance with a circulant matrix. 
     
     
       6. A data loading circuit for a digital micromirror device (DMD), the DMD having a mirror element array coupled to a memory cell array, and the data loading circuit comprising:
 a shadow load register configured to store a current word of a current portion of a pseudorandom pattern of pixels, the pseudorandom pattern being formed by a series of words; 
 a load controller coupled to the shadow load register and adapted to be coupled the memory cell array, the load controller configured to parallel shift the current word from the shadow load register into a current row or column of the memory cell array and, after the parallel shift, designate a next row or column of the memory cell array as the current row or column; and 
 a word pattern generation circuit coupled to the shadow load register, the word pattern generation circuit configured to: generate a next word of a next portion of the pseudorandom pattern based on the current word; and cause the shadow load register to store the next word as the current word; 
 in which the word pattern generation circuit, the shadow load register, and the load controller are configured to respectively generate, store and parallel shift the series of words into the memory cell array until the pseudorandom pattern is fully shifted into the memory cell array for causing the mirror element array to reflect the pseudorandom pattern of pixels from a scene; 
 the shadow load register is configured to store n bits; and 
 the word pattern generation circuit is configured to generate the next word by performing a modulo shift on contents of the shadow load register by serially shifting contents of first through n-1 bits of the shadow load register to second through n bit positions and shifting content of the n bit position to a first bit position. 
 
     
     
       7. A data loading circuit for a digital micromirror device (DMD), the DMD having a mirror element array coupled to a memory cell array, and the data loading circuit comprising:
 a shadow load register configured to store a current word of a current portion of a pseudorandom pattern of pixels, the pseudorandom pattern being formed by a series of words; 
 a load controller coupled to the shadow load register and adapted to be coupled the memory cell array, the load controller configured to parallel shift the current word from the shadow load register into a current row or column of the memory cell array and, after the parallel shift, designate a next row or column of the memory cell array as the current row or column; 
 a word pattern generation circuit coupled to the shadow load register, the word pattern generation circuit configured to: generate a next word of a next portion of the pseudorandom pattern based on the current word; and cause the shadow load register to store the next word as the current word; and 
 a pattern data storage device; 
 in which the word pattern generation circuit, the shadow load register, and the load controller are configured to respectively generate, store and parallel shift the series of words into the memory cell array until the pseudorandom pattern is fully shifted into the memory cell array for causing the mirror element array to reflect the pseudorandom pattern of pixels from a scene; 
 the pseudorandom pattern is based on a select frame of a set of frames that define structured light patterns, each structured light pattern including a known pattern of bars that are perpendicular to an orientation of the shadow load register in relation to the memory cell array; and 
 the word pattern generation circuit is configured to generate the next word by identifying the select frame of the set of frames upon which the pseudorandom pattern is based, selecting a word pattern for the select frame from the pattern data storage device, and parallel shifting the selected word pattern from the pattern data storage device to the shadow load register. 
 
     
     
       8. A data loading circuit for a digital micromirror device (DMD), the DMD having a mirror element array coupled to a memory cell array, and the data loading circuit comprising:
 a shadow load register configured to store a current word of a current portion of a pseudorandom pattern of pixels, the pseudorandom pattern being formed by a series of words; 
 a load controller coupled to the shadow load register and adapted to be coupled the memory cell array, the load controller configured to parallel shift the current word from the shadow load register into a current row or column of the memory cell array and, after the parallel shift, designate a next row or column of the memory cell array as the current row or column; 
 a word pattern generation circuit coupled to the shadow load register, the word pattern generation circuit configured to: generate a next word of a next portion of the pseudorandom pattern based on the current word; and cause the shadow load register to store the next word as the current word; and 
 a pattern data storage device; 
 in which the word pattern generation circuit, the shadow load register, and the load controller are configured to respectively generate, store and parallel shift the series of words into the memory cell array until the pseudorandom pattern is fully shifted into the memory cell array for causing the mirror element array to reflect the pseudorandom pattern of pixels from a scene; 
 the pseudorandom pattern is based on a select frame of a set of frames that define structured light patterns, each structured light pattern including a known pattern of bars that are parallel to an orientation of the shadow load register in relation to the memory cell array; and, 
 the word pattern generation circuit is configured to generate the next word by identifying the select frame of the set of frames upon which the pseudorandom pattern is based, obtaining dimensional factors for the pattern of bars of the select frame from the pattern data storage device, identifying the next word to be generated in the select frame based on incrementally counting words in the select frame, and setting all bits in the shadow load register to “on” or “off” for the next word based on the dimensional factors for the pattern of bars and the incremental counting of words as they are generated. 
 
     
     
       9. A spatial light modulator, comprising:
 a memory cell array; 
 a mirror element array coupled to the memory cell array; and 
 a data loading circuit including:
 a shadow load register configured to store a current word of a current portion of a pseudorandom pattern of pixels, the pseudorandom pattern being formed by a series of words; 
 a load controller coupled to the shadow load register and adapted to be coupled the memory cell array, the load controller configured to parallel shift the current word from the shadow load register into a current row or column of the memory cell array and, after the parallel shift, designate a next row or column of the memory cell array as the current row or column; and 
 a word pattern generation circuit coupled to the shadow load register, the word pattern generation circuit configured to: generate a next word of a next portion of the pseudorandom pattern based on the current word; and cause the shadow load register to store the next word as the current word; 
 
 in which the word pattern generation circuit, the shadow load register, and the load controller are configured to respectively generate, store and parallel shift the series of words into the memory cell array until the pseudorandom pattern is fully shifted into the memory cell array; 
 the memory cell array is configured to cause the mirror element array to reflect the pseudorandom pattern of pixels from a scene; 
 the shadow load register is configured to store n bits; and 
 the word pattern generation circuit is configured to generate the next word by serially shifting contents of first through n- 1  bits of the shadow load register to second through n bit positions and generating content for a first bit position in the shadow load register using a linear feedback shift register (LFSR) that taps select bits of the shadow load register as inputs to an exclusive-OR logic circuit and feeds back an output of the exclusive-OR logic circuit to the first bit position of the shadow load register. 
 
     
     
       10. A spatial light modulator, comprising:
 a memory cell array; 
 a mirror element array coupled to the memory cell array; and 
 a data loading circuit including:
 a shadow load register configured to store a current word of a current portion of a pseudorandom pattern of pixels, the pseudorandom pattern being formed by a series of words; 
 a load controller coupled to the shadow load register and adapted to be coupled the memory cell array, the load controller configured to parallel shift the current word from the shadow load register into a current row or column of the memory cell array and, after the parallel shift, designate a next row or column of the memory cell array as the current row or column; 
 a word pattern generation circuit coupled to the shadow load register, the word pattern generation circuit configured to: generate a next word of a next portion of the pseudorandom pattern based on the current word; and cause the shadow load register to store the next word as the current word; and 
 a pattern data storage device; 
 
 in which the word pattern generation circuit, the shadow load register, and the load controller are configured to respectively generate, store and parallel shift the series of words into the memory cell array until the pseudorandom pattern is fully shifted into the memory cell array; 
 the memory cell array is configured to cause the mirror element array to reflect the pseudorandom pattern of pixels from a scene; 
 the pseudorandom pattern is based on a select frame of a set of frames that define structured light patterns, each structured light pattern including a known pattern of bars that are perpendicular to an orientation of the shadow load register in relation to the memory cell array; and 
 in which the word pattern generation circuit is configured to generate the next word by identifying the select frame of the set of frames upon which the pseudorandom pattern is based, selecting a word pattern for the select frame from the pattern data storage device, and parallel shifting the selected word pattern from the pattern data storage device to the shadow load register. 
 
     
     
       11. The data loading circuit of  claim 1 , wherein the word pattern generation circuit is configured to generate the next word for the shadow load register using a circulant shift mode in accordance with a circulant matrix. 
     
     
       12. The data loading circuit of  claim 3 , further comprising:
 a pattern data storage device coupled to the word pattern generation circuit; 
 in which the word pattern generation circuit is configured to: identify the seed word in the pattern data storage device; and parallel shift the seed word from the pattern data storage device into the shadow load register. 
 
     
     
       13. The data loading circuit of  claim 3 , wherein the word pattern generation circuit is configured to generate the next word for the shadow load register using a circulant shift mode in accordance with a circulant matrix. 
     
     
       14. The data loading circuit of  claim 4 , further comprising:
 a pattern data storage device coupled to the word pattern generation circuit; 
 in which the word pattern generation circuit is configured to: identify the seed word in the pattern data storage device; and parallel shift the seed word from the pattern data storage device into the shadow load register. 
 
     
     
       15. The data loading circuit of  claim 6 , further comprising:
 a pattern data storage device coupled to the word pattern generation circuit; 
 in which the word pattern generation circuit is configured to: identify the seed word in the pattern data storage device; and parallel shift the seed word from the pattern data storage device into the shadow load register. 
 
     
     
       16. The data loading circuit of  claim 6 , wherein the word pattern generation circuit is configured to generate the next word for the shadow load register using a circulant shift mode in accordance with a circulant matrix. 
     
     
       17. The data loading circuit of  claim 7 , further comprising:
 a pattern data storage device coupled to the word pattern generation circuit; 
 in which the word pattern generation circuit is configured to: identify the seed word in the pattern data storage device; and parallel shift the seed word from the pattern data storage device into the shadow load register. 
 
     
     
       18. The data loading circuit of  claim 7 , wherein the word pattern generation circuit is configured to generate the next word for the shadow load register using a circulant shift mode in accordance with a circulant matrix. 
     
     
       19. The data loading circuit of  claim 8 , further comprising:
 a pattern data storage device coupled to the word pattern generation circuit; 
 in which the word pattern generation circuit is configured to: identify the seed word in the pattern data storage device; and parallel shift the seed word from the pattern data storage device into the shadow load register. 
 
     
     
       20. The data loading circuit of  claim 8 , wherein the word pattern generation circuit is configured to generate the next word for the shadow load register using a circulant shift mode in accordance with a circulant matrix.