Optimizing memory fences based on workload

Abstract

A method, computer program product, and apparatus for optimizing memory fences based on workload are provided. The method includes determining whether to execute a target program on a single hardware thread or a plurality of hardware threads. The method also includes assigning one of a light-weight memory fence and a heavy-weight memory fence as a memory fence in the target program based on whether to execute the target program on the single hardware thread or the plurality of hardware threads. The method further includes assigning the light-weight memory fence in response to determining to execute the target program on the single hardware thread, and the heavy-weight memory fence is assigned in response to determining to execute the target program on the plurality of hardware threads.

What is claimed is: 
     
       1. A computer-implemented method comprising:
 determining whether to execute a target program on a single hardware thread or a plurality of hardware threads; and 
 assigning one of a light-weight memory fence and a heavy-weight memory fence as a memory fence in the target program based on whether to execute the target program on the single hardware thread or the plurality of hardware threads, wherein at least one of the light-weight memory fence and the heavy-weight memory fence are configured to provide memory access based on visibility; 
 wherein the light-weight memory fence is assigned in response to determining to execute the target program on the single hardware thread, and the heavy-weight memory fence is assigned in response to determining to execute the target program on the plurality of hardware threads. 
 
     
     
       2. The computer-implemented method of  claim 1 , wherein the light-weight memory fence is configured to guarantee that every memory access of a predetermined type preceding the light-weight memory fence in program order is locally visible in the single hardware thread before allowing any memory access of the predetermined type following the light-weight memory fence in program order. 
     
     
       3. The computer-implemented method of  claim 1 , wherein the heavy-weight memory fence is configured to guarantee that every memory access of a predetermined type preceding the heavy-weight memory fence in program order is globally visible in the plurality of hardware threads before allowing any memory access of the predetermined type following the heavy-weight memory fence in program order. 
     
     
       4. The computer-implemented method of  claim 1 , wherein the assigning the light-weight memory fence includes replacing a heavy-weight memory fence instruction in the target program with a light-weight memory fence instruction. 
     
     
       5. The computer-implemented method of  claim 4 , wherein the assigning the heavy-weight memory fence further includes restoring, after the target program is executed on the single hardware thread, the heavy-weight memory fence instruction in the target program in response to determining to execute the target program on a plurality of hardware threads. 
     
     
       6. The computer-implemented method of  claim 4 , wherein the assigning the light-weight memory fence includes replacing the heavy-weight memory fence instruction with a no operation in response to a condition that the processor executing the target program is configured to guarantee that every memory access of a predetermined type is locally visible in the single hardware thread before any subsequent memory accesses of the predetermined type in program order are performed. 
     
     
       7. The computer-implemented method of  claim 1 , further comprising inserting, to the target program, a code for conditionally executing the heavy-weight memory fence;
 wherein the assigning the heavy-weight memory fence includes setting a condition of the code to execute the heavy-weight memory fence. 
 
     
     
       8. The computer-implemented method of  claim 1 , further comprising:
 preparing a first version of the target program including the heavy-weight memory fence and a second version of the target program including the light-weight memory fence; and 
 wherein the assigning the heavy-weight memory fence further includes specifying that the first version of the target program is selected to be executed, and 
 the assigning the light-weight memory fence includes specifying that the second version of the target program is selected to be executed. 
 
     
     
       9. The computer-implemented method of  claim 1 , further comprising monitoring an execution workload of the target program;
 wherein the determining includes determining whether to execute the target program on the single hardware thread or the plurality of hardware threads based on the execution workload. 
 
     
     
       10. The computer-implemented method of  claim 9 , wherein the determining includes determining to execute the target program on the single hardware thread in response to the execution workload being lower than a first threshold, the first threshold not being more than a processing capacity of the single hardware thread. 
     
     
       11. The computer-implemented method of  claim 10 , wherein the determining includes determining to execute the target program on the plurality of hardware threads in response to the execution workload not being lower than a second threshold. 
     
     
       12. The computer-implemented method of  claim 1 , further comprising switching execution of the target program between execution on the single hardware thread and execution on the plurality of hardware threads during temporary suspension of execution of the target program. 
     
     
       13. The computer-implemented method of  claim 12 , wherein the temporary suspension of execution of the target program is caused by a garbage collection. 
     
     
       14. The computer-implemented method of  claim 12 , wherein the switching includes setting a processor affinity of software threads of the target program to the single hardware thread in response to determining to execute the target program on the single hardware thread. 
     
     
       15. A computer program product including one or more computer readable storage mediums correctively storing program instructions that are executable by a processor or programmable circuitry to cause the processor or programmable circuitry to perform operations comprising:
 determining whether to execute a target program on a single hardware thread or a plurality of hardware threads; and 
 assigning one of a light-weight memory fence and a heavy-weight memory fence as a memory fence in the target program based on whether to execute the target program on the single hardware thread or the plurality of hardware threads, wherein at least one of the light-weight memory fence and the heavy-weight memory fence are configured to provide memory access based on visibility; 
 wherein the light-weight memory fence is assigned in response to determining to execute the target program on the single hardware thread, and the heavy-weight memory fence is assigned in response to determining to execute the target program on the plurality of hardware threads. 
 
     
     
       16. The computer program product of  claim 15 , wherein the assigning the light-weight memory fence includes replacing a heavy-weight memory fence instruction in the target program with a light-weight memory fence instruction. 
     
     
       17. The computer program product of  claim 15 , wherein the operations further comprising monitoring an execution workload of the target program;
 wherein the determining includes determining whether to execute the target program on the single hardware thread or the plurality of hardware threads based on the execution workload. 
 
     
     
       18. An apparatus comprising:
 a processor or a programmable circuitry, and 
 one or more computer readable mediums collectively including instructions that, when executed by the processor or the programmable circuitry, cause the processor or the programmable circuitry to: 
 determine whether to execute a target program on a single hardware thread or a plurality of hardware threads; and 
 assign one of a light-weight memory fence and a heavy-weight memory fence as a memory fence in the target program based on whether to execute the target program on the single hardware thread or the plurality of hardware threads, wherein at least one of the light-weight memory fence and the heavy-weight memory fence are configured to provide memory access based on visibility; 
 wherein the light-weight memory fence is assigned in response to determining to execute the target program on the single hardware thread, and the heavy-weight memory fence is assigned in response to determining to execute the target program on the plurality of hardware threads. 
 
     
     
       19. The apparatus of  claim 18 , wherein the assigning the light-weight memory fence includes replacing a heavy-weight memory fence instruction in the target program with a light-weight memory fence instruction. 
     
     
       20. The apparatus of  claim 18 , wherein the instructions further causes the processor or the programmable circuitry to monitor an execution workload of the target program;
 wherein the determining includes determining whether to execute the target program on the single hardware thread or the plurality of hardware threads based on the execution workload.