Semiconductor memory device

Abstract

According to one embodiment, a semiconductor memory device includes a substrate, a plurality of electrode films arranged along a first direction with an air gap interposed, the first direction crossing a surface of the substrate, a semiconductor member extending in the first direction, a charge storage member provided between the semiconductor member and each of the electrode films, and a high dielectric constant film provided along an outer surface of the air gap, a relative dielectric constant of the high dielectric constant film being higher than a relative dielectric constant of silicon oxide.

What is claimed is: 
     
       1. A semiconductor memory device, comprising:
 a substrate; 
 a plurality of electrode films arranged along a first direction with an air gap interposed, the first direction crossing a surface of the substrate; 
 a semiconductor member extending in the first direction; 
 a charge storage member provided between the semiconductor member and each of the electrode films; and 
 a high dielectric constant film provided along an outer surface of the air gap, a relative dielectric constant of the high dielectric constant film being higher than a relative dielectric constant of silicon oxide, 
 wherein the high dielectric constant film is formed to be continuous along a surface of a structure body, the structure body including two electrode films of the plurality of electrode films adjacent to each other in the first direction, the semiconductor member, and two charge storage members disposed respectively between the semiconductor member and the two electrode films. 
 
     
     
       2. The device according to  claim 1 , wherein in a cross section along the first direction, curvatures of high dielectric constant film surface portions exposed in the air gap at positions between a portion of the high dielectric constant film formed along a side surface of the semiconductor member and portions of the high dielectric constant film formed along surfaces of the two electrode films are smaller than curvatures of corner portions where the side surface of the semiconductor member crosses extension planes of the surfaces of the two electrode films. 
     
     
       3. The device according to  claim 1 , further comprising a first insulating film provided between the high dielectric constant film and the two electrode films, between the high dielectric constant film and the two charge storage members, and between the semiconductor member and the high dielectric constant film, an energy barrier of the first insulating film being higher than an energy barrier of the high dielectric constant film. 
     
     
       4. The device according to  claim 3 , wherein the first insulating film includes silicon oxide. 
     
     
       5. The device according to  claim 1 , wherein the high dielectric constant film contacts the semiconductor member. 
     
     
       6. The device according to  claim 1 , further comprising a second insulating film provided between the semiconductor member and the charge storage member, the high dielectric constant film being separated from the semiconductor member with at least a portion of the second insulating film interposed. 
     
     
       7. The device according to  claim 1 , wherein a positive charge is stored in a portion of the high dielectric constant film disposed between the semiconductor member and the air gap. 
     
     
       8. The device according to  claim 1 , wherein a p-n junction is not formed in a portion of the semiconductor member opposing the plurality of electrode films and the air gap. 
     
     
       9. The device according to  claim 1 , wherein the plurality of electrode films each surrounds the semiconductor member. 
     
     
       10. A semiconductor memory device, comprising:
 a substrate; 
 a semiconductor member extending in a first direction and formed above the substrate, the first direction crossing a surface of the substrate; 
 a first cell gate layer including a first control electrode and a first charge storage portion and being disposed to oppose a side surface of the semiconductor member, the first charge storage portion being provided between the first control electrode and the semiconductor member; 
 a second cell gate layer including a second control electrode and a second charge storage portion and being disposed to oppose the side surface of the semiconductor member between the substrate and the first cell gate layer, the second charge storage portion being provided between the second control electrode and the semiconductor member; and 
 an insulating film including a high dielectric constant film formed between the first cell gate layer and the second cell gate layer, 
 the insulating film including a first portion, a second portion, and a third portion, the first portion being along a lower surface of the first cell gate layer, the second portion being along an upper surface of the second cell gate layer, the third portion being along the side surface of the semiconductor member, an air gap being disposed between the first portion and the second portion. 
 
     
     
       11. The device according to  claim 10 , wherein the first portion, the second portion, and the third portion are formed continuously. 
     
     
       12. The device according to  claim 11 , wherein in a cross section along the first direction, a curvature of an insulating film surface portion exposed in the air gap at a position between the second portion and the third portion is smaller than a curvature of a corner portion where the side surface of the semiconductor member crosses an extension plane of the upper surface of the second cell gate layer. 
     
     
       13. The device according to  claim 11 , wherein the insulating film further includes a first insulating film provided at least between the first charge storage portion and the high dielectric constant film, between the second charge storage portion and the high dielectric constant film, and between the semiconductor member and the high dielectric constant film, an energy barrier of the first insulating film being higher than an energy barrier of the high dielectric constant film. 
     
     
       14. The device according to  claim 13 , wherein
 a relative dielectric constant of the high dielectric constant film is higher than a relative dielectric constant of silicon oxide, and 
 the first insulating film includes silicon oxide. 
 
     
     
       15. The device according to  claim 10 , wherein the insulating film contacts the side surface of the semiconductor member. 
     
     
       16. The device according to  claim 10 , wherein
 the first and second cell gate layers both further include a second insulating film provided on the side surface of the semiconductor member, and 
 the insulating film is separated from the semiconductor member with at least a portion of the second insulating film interposed. 
 
     
     
       17. The device according to  claim 10 , wherein a positive charge is stored in the third portion of the insulating film. 
     
     
       18. The device according to  claim 10 , wherein a p-n junction is not formed in a portion of the semiconductor member opposing the first cell gate layer, the second cell gate layer, and the insulating film. 
     
     
       19. The device according to  claim 10 , wherein the first cell gate layer and the second cell gate layer each surround the semiconductor member. 
     
     
       20. A semiconductor memory device, comprising:
 a substrate; 
 a plurality of electrode films arranged along a first direction with an air gap interposed, the first direction crossing a surface of the substrate; 
 a semiconductor member extending in the first direction; 
 a charge storage member provided between the semiconductor member and each of the electrode films; and 
 a high dielectric constant film provided along an outer surface of the air gap, a relative dielectric constant of the high dielectric constant film being higher than a relative dielectric constant of silicon oxide, and 
 wherein a p-n junction is not formed in a portion of the semiconductor member opposing the plurality of electrode films and the air gap.