Shift register and display device comprising the same

Abstract

A bi-directional shift register can include a plurality of stages, an N th stage among the plurality of stages including a first switching unit configured to receive a forward driving signal and a reverse driving signal, and control a Q-node; a second switching unit configured to receive an (N+2) th clock signal, and control a QB-node; a third switching unit configured to discharge the QB-node to a low-level voltage when the Q-node is charged to a high-level voltage, and discharge the Q-node to the low-level voltage when the QB-node is charged to the high-level voltage; and an output unit configured to output an N th clock signal to an output terminal based on a voltage at the Q-node, in which the forward driving signal is an output signal from an (N−1) th stage or a forward start signal from an external source external to the shift register, and the reverse driving signal is an output signal from the (N+1) th stage or a reverse start signal from the external source.

What is claimed is: 
     
       1. A shift register comprising:
 a plurality of stages, an N th  stage among the plurality of stages including:
 a first switching unit configured to receive a forward driving signal and a reverse driving signal, and control a Q-node; 
 a second switching unit configured to receive an (N+3) th  clock signal, control a QB-node, where N is a positive number; 
 a third switching unit configured to discharge the QB-node to a low-level voltage when the Q-node is charged to a high-level voltage, and discharge the Q-node to the low-level voltage when the QB-node is charged to the high-level voltage; 
 a first output unit configured to output an N th  clock signal to a first output terminal based on a voltage at the Q-node; and 
 a second output unit configured to output an (N+1) th  clock signal to a second output terminal based on the voltage at the Q-node. 
 
 
     
     
       2. The shift register of  claim 1 , wherein the forward driving signal is an output signal from an (N−1) th  stage among the plurality of stages or a forward start signal from an external source external to the shift register, and
 wherein the reverse driving signal is an output signal from the (N+1) th  stage among the plurality of stages or a reverse start signal from the external source. 
 
     
     
       3. The shift register of  claim 1 , wherein the first switching unit comprises:
 a forward driving transistor having a gate electrode configured to receive the forward driving signal, a drain electrode configured to receive the high-level voltage, and a source electrode connected to the Q-node; and 
 a reverse driving transistor having a gate electrode configured to receive the reverse driving signal, a drain electrode configured to receive the high-level voltage, and a source electrode connected to the Q-node, and 
 wherein the second switching unit comprises: 
 a pull-down transistor having a gate electrode configured to receive the (N+3) th  clock signal, a drain electrode configured to receive the high-level voltage, and a source electrode connected to the QB-node. 
 
     
     
       4. The shift register of  claim 1 , wherein the third switching unit comprises:
 a first switching transistor having a gate electrode connected to the Q-node, a drain electrode configured to receive the low-level voltage, and a source electrode connected to the QB-node; and 
 a second switching transistor having a gate electrode connected to the QB-node, a drain electrode configured to receive the low-level voltage, and a source electrode connected to the Q-node. 
 
     
     
       5. The shift register of  claim 2 , further comprising:
 a fourth switching unit comprising a third switching transistor having a gate electrode configured to receive the high-level voltage, a drain electrode connected to the Q-node, and a source electrode connected to the first output unit. 
 
     
     
       6. The shift register of  claim 2 , wherein the first output unit comprises:
 a first buffer transistor having a gate electrode configured to receive the voltage at the Q-node, a drain electrode configured to receive the N th  clock signal, and a source electrode connected to the first output terminal; and 
 a second buffer transistor having a gate electrode connected to the QB-node, a drain electrode configured to receive the low-level voltage, and a source electrode connected to the first output terminal. 
 
     
     
       7. The shift register of  claim 2 , wherein the second output unit comprises:
 a third buffer transistor having a gate electrode configured to receive the voltage at the Q-node, a drain electrode configured to receive the (N+1) th  clock signal, and a source electrode connected to the second output terminal; and 
 a fourth buffer transistor having a gate electrode connected to the QB-node, a drain electrode configured to receive the low-level voltage, and a source electrode connected to the second output terminal. 
 
     
     
       8. The shift register of  claim 7 , further comprising:
 a second capacitor connected between the gate electrode of the third buffer transistor and the second output terminal. 
 
     
     
       9. The shift register of  claim 2 , further comprising:
 an abnormal operation correcting unit including:
 a first abnormal operation transistor having a gate electrode configured to receive an abnormal operation signal, a drain electrode configured to receive the abnormal operation signal, and a source electrode connected to the first output terminal of the first output unit and the second output terminal of the second output unit; and 
 a second abnormal operation transistor having a gate electrode configured to receive the abnormal operation signal, a drain electrode configured to receive the low-level voltage, and a source electrode connected to the QB-node. 
 
 
     
     
       10. The shift register of  claim 9 , wherein the abnormal operation correcting unit further includes:
 a third abnormal operation transistor having a gate electrode configured to receive the abnormal operation signal, a drain electrode configured to receive the low-level voltage, and a source electrode connected to the output terminal of the first output unit and the second output terminal of the second output unit.