Circuit configuration optimization apparatus and machine learning device

Abstract

A circuit configuration optimization apparatus includes a machine learning device that learns a circuit configuration of a FPGA device. The machine learning device observes circuit configuration data of the FPGA device and FPGA error occurrence state data indicating an error occurrence state of the FPGA device as state variables that express a current state of an environment. In addition, the machine learning device acquires determination data indicating propriety determination results of an operating state of the FPGA device. Then, the machine learning device learns the circuit configuration of the FPGA device in association with the FPGA error occurrence state data, using the state variables and the determination data.

The invention claimed is: 
     
       1. A circuit configuration optimization apparatus that optimizes a circuit configuration and an arrangement of a field programmable gate array (FPGA) device, the circuit configuration optimization apparatus comprising:
 a machine learning device that learns the circuit configuration of the FPGA device, wherein the machine learning device includes 
 a state observation section that observes, as state variables that express a current state of an environment, circuit configuration data of the FPGA device indicating the circuit configuration of the FPGA device, and FPGA error occurrence state data indicating an error occurrence state of the FPGA device which includes soft error occurrence frequencies at the respective positions of the EPGA device, 
 a determination data acquisition section that acquires determination data indicating propriety determination results of an operating state of the FPGA device, and 
 a learning section that learns the circuit configuration of the FPGA device in association with the FPGA error occurrence state data, using the state variables and the determination data. 
 
     
     
       2. The circuit configuration optimization apparatus according to  claim 1 , wherein
 the state observation section further observes FPGA device operating state data containing, as the state variable, at least any of a heating value, power consumption, and operating speed of the FPGA device, and 
 the learning section learns the circuit configuration of the FPGA device in association with both the FPGA error occurrence state data and the FPGA device operating state data. 
 
     
     
       3. The circuit configuration optimization apparatus according to  claim 1 , wherein
 the learning section includes
 a reward calculation section that calculates rewards relating to the propriety determination results, and 
 a value function update section that updates, using the rewards, a function that expresses values of the circuit configuration of the FPGA device for the error occurrence state of the FPGA device. 
 
 
     
     
       4. The circuit configuration optimization apparatus according to  claim 1 , wherein
 the learning section calculates the state variables and the determination data in a multilayer neural network. 
 
     
     
       5. The circuit configuration optimization apparatus according to  claim 1 , further comprising a decision-making section that outputs a command value based on the circuit configuration of the FPGA device, according to learning results of the learning section. 
     
     
       6. The circuit configuration optimization apparatus according to  claim 1 , wherein
 the learning section learns the circuit configuration of the FPGA device in each of a plurality of industrial machines, using the state variables and the determination data obtained for each of the plurality of industrial machines. 
 
     
     
       7. The circuit configuration optimization apparatus according to  claim 1 , wherein
 the machine learning device exists in a cloud server. 
 
     
     
       8. A machine learning device that learns a circuit configuration of a FPGA device, the machine learning device comprising:
 a state observation section that observes, as state variables that express a current state of an environment, circuit configuration data of the FPGA device indicating the circuit configuration of the FPGA device, and FPGA error occurrence state data indicating an error occurrence state of the FPGA device which includes soft error occurrence frequencies at the respective positions of the EPGA device; 
 a determination data acquisition section that acquires determination data indicating propriety determination results of an operating state of the FPGA device; and 
 a learning section that learns the circuit configuration of the FPGA device in association with the FPGA error occurrence state data, using the state variables and the determination data.