Low resistance contact method and structure

Abstract

A device includes a metal-silicide region formed in a semiconductor material in a contact opening. A concentration of a material, including chlorine, fluorine, or a combination thereof is in the metal-silicide region near an uppermost surface of the metal-silicide region. The presence of chlorine or fluorine results from a physical bombarding of the chlorine or fluorine in the contact opening. As a result of the physical bombard, the opening becomes wider at the bottom of the opening and the sidewalls of the opening are thinned. A capping layer is over the metal-silicide region and over sidewalls of a contact plug opening. A contact plug is formed over the capping layer, filling the contact plug opening. Before the contact plug is formed, a silicidation occurs to form the metal-silicide and the metal-silicide is wider than the bottom of the opening.

What is claimed is: 
     
       1. A method, comprising:
 forming an opening in an insulating layer between a first gate and a second gate, the opening exposing a contact area of a source/drain region; 
 cleaning the opening; 
 bombarding a bottom of the opening with a first material, thereby causing a chemical reaction between the first material and a top surface of the contact area; 
 depositing a metal layer in the opening; 
 depositing a capping layer over the metal layer; 
 creating a silicide at the top surface of the contact area, the silicide having a first depth, wherein an upper surface of the silicide includes a first concentration of the first material, wherein the first concentration of the first material in the silicide decreases by a first gradient to a second concentration of the first material at a second depth of the silicide, wherein the silicide has the second concentration from the second depth of the silicide to the first depth of the silicide, wherein the second depth is interposed between the top surface of the silicide and the first depth of the silicide; 
 after creating the silicide, depositing a metal plug in the opening. 
 
     
     
       2. The method of  claim 1 , further comprising:
 planarizing the metal plug so that an uppermost surface of the metal plug is substantially coplanar with an uppermost surface of the first gate and an uppermost surface of the second gate. 
 
     
     
       3. The method of  claim 1 , wherein the silicide is wider than a bottom width of the opening, the width extending under a first spacer of the first gate and under a second spacer of the second gate. 
     
     
       4. The method of  claim 1 , wherein the cleaning and the bombarding are done simultaneously. 
     
     
       5. The method of  claim 1 , wherein the first depth of the silicide is between 6 nm and a thickness of the source/drain region. 
     
     
       6. The method of  claim 1 , wherein the first material comprises ammonia. 
     
     
       7. The method of  claim 1 , wherein the insulating layer comprises a continuous layer that laterally surrounds the first and second gate and extends over a top of the first gate and over a top of the second gate, wherein a thickness of the insulating layer is greater than a height of the first gate, wherein the opening exposes a first mask layer over a first gate electrode of the first gate and a second mask layer over a second gate electrode of the second gate, and wherein the bombarding includes bombarding the first mask layer and the second mask layer. 
     
     
       8. The method of  claim 1 , wherein the bombarding causes the opening to widen at the bottom of the opening so that a ratio of a first width at the bottom of the opening to a second width of the opening at a vertical midpoint of the first gate is greater than 90%. 
     
     
       9. A method, comprising:
 forming a first gate structure and a second gate structure over a semiconductor fin in a direction perpendicular to the semiconductor fin, the first gate structure comprising a first gate stack and a first gate spacer disposed next to the first gate stack, the second gate structure comprising a second stack and a second gate spacer next to the second gate stack, the first gate spacer and second gate spacer each having a non-vertical sidewall; 
 depositing a first layer between the first gate spacer and the second gate spacer, the first layer comprising a dielectric material; 
 etching an opening in the first layer to expose a source/drain region of a transistor, wherein the etching uses the first gate spacer of the first gate structure and the second gate spacer of the second gate structure as an etch mask; 
 enlarging the opening by a cleaning process; 
 bombarding the exposed source/drain region with a first material, the first material reacting with a material of the source/drain region, wherein the bombarding causes the non-vertical sidewall of the first gate spacer and the non-vertical sidewall of the second gate spacer to become more vertical, wherein after bombarding the exposed source/drain region a ratio of a first width at a bottom of the opening to a second width of the opening at a vertical midpoint of the first gate structure is greater than 90%; 
 depositing a metal film in the opening; and 
 siliciding the source/drain region to form a silicide region in the source/drain region, wherein a first concentration of the first material in the silicide region decreases in a gradient further from the upper surface of the silicide region until an intermediate location of the silicide region, wherein a second concentration of the first material in the silicide region is substantially uniform from the intermediate location of the silicide region to a depth of the silicide region. 
 
     
     
       10. The method of  claim 9 , further comprising:
 prior to siliciding the source/drain region, forming a capping layer over the metal film. 
 
     
     
       11. The method of  claim 10 , further comprising:
 forming a metal plug in the opening, wherein following the forming the metal plug, the capping layer remains interposed between the metal plug and the silicide region. 
 
     
     
       12. The method of  claim 9 , wherein the cleaning process and bombarding are performed in a same process step. 
     
     
       13. The method of  claim 9 , wherein the first material comprises fluorine, chlorine, or a combination thereof. 
     
     
       14. The method of  claim 9 , further comprising:
 forming a third gate spacer interposed between the first gate spacer and the first gate stack; and 
 forming a fourth gate spacer interposed between the second gate spacer and the second gate stack, wherein the silicide region extends horizontally beyond lateral extents of the opening, wherein the silicide region extends under the first gate spacer to the third gate spacer and under the second gate spacer to the fourth gate spacer. 
 
     
     
       15. The method of  claim 9 , wherein the first material comprises ammonia. 
     
     
       16. A method, comprising:
 forming a source/drain region between a first gate stack and a second gate stack; 
 forming an insulating layer over the source/drain region, the insulating layer extending over the first gate stack and the second gate stack; 
 etching an opening in the insulating layer, the opening exposing the source/drain region, an upper portion of the first gate stack, and an upper portion of the second gate stack; 
 bombarding the source/drain region with a first material, the first material comprising chlorine; and 
 forming a silicide region at an upper portion of the source/drain region, the silicide region extending laterally further than the opening, an upper surface of the silicide region including a first concentration of the first material, wherein the first concentration of the first material in the silicide region decreases in a gradient further from the upper surface of the silicide region until an intermediate location of the silicide region, wherein a second concentration of the first material in the silicide region is substantially uniform from the intermediate location of the silicide region to a depth of the silicide region. 
 
     
     
       17. The method of  claim 16 , wherein forming the silicide region comprises:
 depositing a first metal film in the opening, the first metal film contacting the source/drain region; 
 depositing a capping layer in the opening over the first metal film; and 
 annealing the source/drain region. 
 
     
     
       18. The method of  claim 16 , further comprising:
 depositing a metal plug in the opening, wherein a third concentration of the first material is disposed in the metal plug; and 
 planarizing the metal plug and insulating layer to level an uppermost surface of the metal plug with an uppermost surface of the first gate stack. 
 
     
     
       19. The method of  claim 16 , further comprising:
 in conjunction with the bombarding the source/drain region, enlarging the opening through a cleaning etch process. 
 
     
     
       20. The method of  claim 16 , wherein, the bombarding causes a first non-vertical sidewall of the opening to become more vertical, the first non-vertical sidewall of the opening including a spacer of the first gate stack.