Techniques for access control using wearable devices
Abstract
Various embodiments are generally directed to techniques for using little or no electric power to monitor whether a wearable device continues to be worn by a person such that it may continue to be used to access a secured item. An apparatus may include a processor component; a storage to store an access credential; a presentation component to wirelessly transmit the access credential to an access device to enable a grant of access to a secured item; a power source; and a clasp coupled to a wearable portion to prevent removal of the wearable portion unless the clasp is operated to change state from a clasped state to an unclasped state, the clasp to cause loss of electric power from the power source to the processor component and the storage when in the unclasped state to nullify the access credential. Other embodiments are described and claimed.
Claims
exact text as granted — not AI-modifiedThe invention claimed is:
1. A wearable apparatus comprising:
a clasp operable between a clasped state and an unclasped state, the clasped state to place a switch in a first position and the unclasped state to place the switch in a second position;
a transistor comprising first, second, and third terminals, the first terminal connected in parallel with the switch and a positive terminal of a power source, the second terminal connected to a power input of a processor component, and the third terminal connected in parallel with the switch and a tamper signal input to the processor component;
a memory communicatively coupled with the processor component, the memory comprising data; and
logic, at least a portion of the logic implemented by the processor component, the logic to:
identify a voltage change at the tamper signal input in response to operation of the clasp from the clasped state to the unclasped state; and
alter one or more portions of the data in response to the voltage change.
2. The wearable apparatus of claim 1 , operation of the clasp from the clasped state to the unclasped state to cause a voltage drop at the power input to the processor component.
3. The wearable apparatus of claim 2 , operation of the clasp from the clasped state to the unclasped state to cause a voltage change at the third terminal, the voltage change at the third terminal to cause the voltage drop at the power input to the processor component.
4. The wearable apparatus of claim 1 , the third terminal connected in parallel with a resistor connected to a negative terminal of the power source.
5. The wearable apparatus of claim 1 , the logic to erase or overwrite the one or more portions of the data to alter the one or more portions of the data in response to the voltage change.
6. The wearable apparatus of claim 5 , the one or more portions of the data comprising access credentials.
7. The wearable apparatus of claim 1 , comprising:
an antenna; and
an interface to couple the processor component to the antenna to provide the processor component with electric power conveyed to the antenna via an electromagnetic field.
8. The wearable apparatus of claim 1 , comprising:
an antenna; and
an interface to couple the processor component to the antenna, the logic to retrieve an identifier from the memory and cooperate with the interface to transmit the identifier via near field communications (NFC) to an initialization device.
9. The wearable apparatus of claim 8 , the logic to receive the data via NFC in response to transmission of the identifier to the initialization device and store the data in the memory.
10. The wearable apparatus of claim 9 , the logic to condition transmission of the data on whether the clasp has changed state from the clasped state to the unclasped state following receipt of the data via NFC and storage of the data within the memory.
11. The wearable apparatus of claim 8 , the logic to cooperate with the interface to transmit an indication of the state of the clasp to the initialization device via NFC.
12. A method comprising:
measuring a voltage level of a positive terminal of a power source at a tamper input signal of a processor component when a switch is in a first position, the switch connected to a first terminal of a transistor in parallel with the positive terminal of the power source, a second terminal of the transistor connected to a power input of the processor component, and a third terminal of the transistor connected in parallel with the switch and the tamper signal input to the processor component;
determining a clasp is in a clasped state based on the voltage level measured at the tamper input signal of the processor component;
measuring a reference voltage level at the tamper input signal of the processor component in response to operation of the switch into a second position;
determining the clasp is in an unclasped state based on the reference voltage level measured at the tamper input signal of the processor component; and
altering one or more portions of data in a memory communicatively coupled with the processor component in response to determining the clasp is in the unclasped state.
13. The method of claim 12 , operation of the clasp from the clasped state to the unclasped state to cause a voltage drop at the power input to the processor component.
14. The method of claim 13 , operation of the clasp from the clasped state to the unclasped state to cause a voltage change at the third terminal, the voltage change at the third terminal to cause the voltage drop at the power input to the processor component.
15. The method of claim 12 , the third terminal connected in parallel with a resistor connected to a negative terminal of the power source.
16. The method of claim 12 , comprising erasing or overwriting the one or more portions of the data to alter the one or more portions of the data in response to the voltage change.
17. The method of claim 16 , the one or more portions of the data comprising access credentials.
18. The method of claim 12 , comprising providing the processor component with electric power conveyed to an antenna via an electromagnetic field, the antenna coupled to the processor component via an interface.
19. At least one non-transitory computer-readable medium comprising a set of instructions that, in response to being executed by a processor component, cause the processor component to:
measure a voltage level of a positive terminal of a power source at a tamper input signal of a processor component when a switch is in a first position, the switch connected to a first terminal of a transistor in parallel with the positive terminal of the power source, a second terminal of the transistor connected to a power input of the processor component, and a third terminal of the transistor connected in parallel with the switch and the tamper signal input to the processor component;
determine a clasp is in a clasped state based on the voltage level measured at the tamper input signal of the processor component;
measure a reference voltage level at the tamper input signal of the processor component in response to operation of the switch into a second position;
determine the clasp is in an unclasped state based on the reference voltage level measured at the tamper input signal of the processor component; and
altering one or more portions of data in a memory communicatively coupled with the processor component in response to determining the clasp is in the unclasped state.
20. The at least one non-transitory computer-readable medium of claim 19 , comprising instructions that, in response to being executed by the processor component, cause the processor component to retrieve an identifier from the memory and cooperate with an interface to transmit the identifier via near field communications (NFC) to an initialization device.
21. The at least one non-transitory computer-readable medium of claim 20 , comprising instructions that, in response to being executed by the processor component, cause the processor component to receive the data via NFC in response to transmission of the identifier to the initialization device and store the data in the memory.
22. The at least one non-transitory computer-readable medium of claim 21 , comprising instructions that, in response to being executed by the processor component, cause the processor component to condition transmission of the data on whether the clasp has changed state from the clasped state to the unclasped state following receipt of the data via NFC and storage of the data within the memory.
23. The at least one non-transitory computer-readable medium of claim 20 , comprising instructions that, in response to being executed by the processor component, cause the processor component to cooperate with the interface to transmit an indication of the state of the clasp to the initialization device via NFC.
24. The at least one non-transitory computer-readable medium of claim 19 , operation of the clasp from the clasped state to the unclasped state to cause a voltage drop at the power input to the processor component.
25. The at least one non-transitory computer-readable medium of claim 24 , operation of the clasp from the clasped state to the unclasped state to cause a voltage change at the third terminal, the voltage change at the third terminal to cause the voltage drop at the power input to the processor component.Join the waitlist — get patent alerts
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