Control circuit for controlling reset operation

Abstract

A control circuit includes a reset circuit and a determination circuit. The reset circuit is coupled to a digital frequency divider of a phase locked loop circuit and configured to perform a reset operation. The determination circuit is coupled to the reset circuit and configured to determine whether a first predetermined time interval has elapsed so as to control the reset circuit to stop performing the reset operation when the first predetermined time interval has elapsed.

What is claimed is: 
     
       1. A control circuit, comprising:
 a reset circuit coupled to a digital frequency divider of a phase locked loop circuit and configured to perform a reset operation; and 
 a determination circuit coupled to the reset circuit and configured to determine whether a first predetermined time interval has elapsed so as to control the reset circuit to stop performing the reset operation when the first predetermined time interval has elapsed; 
 wherein the phase locked loop circuit further comprises an analog frequency divider coupled to the digital frequency divider, and the first predetermined time interval corresponds to a time required for the analog frequency divider to stabilize; 
 the determination circuit determines whether the first predetermined time interval has elapsed by counting; 
 the phase locked loop circuit further comprises an oscillation source; 
 the control circuit further comprises:
 an operation voltage generation circuit, comprising:
 an output terminal coupled to the analog frequency divider; and 
 
 a first capacitor, comprising:
 a first terminal coupled to the output terminal of the operation voltage generation circuit; and 
 a second terminal coupled to the oscillation source; 
 
 
 the reset circuit comprises:
 an output terminal configured to perform the reset operation or stop the reset operation; and 
 the first predetermined time interval corresponds to the time required for a voltage of the first terminal of the first capacitor to reach a ratio of a predetermined voltage; and 
 
 the operation voltage generation circuit further comprises a bias voltage generator configured to provide a bias voltage to charge the first capacitor. 
 
     
     
       2. The control circuit of  claim 1 , wherein performing the reset operation comprises:
 transmitting at least one reset signals each having a pulse waveform to the digital frequency divider continually; 
 keeping a reset signal being transmitted to the digital frequency divider to be at an enabling level; or 
 transmitting at least one reset signal to the digital frequency divider after the analog frequency divider of the phase locked loop circuit has stabilized and before the first predetermined time interval has elapsed. 
 
     
     
       3. The control circuit of  claim 2 , wherein stopping performing the reset operation comprises stopping transmitting the reset signal to the digital frequency divider. 
     
     
       4. The control circuit of  claim 1 , wherein:
 the bias voltage generator comprises:
 an output terminal configured to provide the bias voltage, wherein the bias voltage is a stable value substantially; and 
 
 the operation voltage generation circuit further comprises: 
 a first resistor, comprising:
 a first terminal coupled to the output terminal of the operation voltage generation circuit; and 
 a second terminal coupled to the output terminal of the bias voltage generator and configured to receive the bias voltage. 
 
 
     
     
       5. The control circuit of  claim 1 , wherein:
 the determination circuit comprises a flip flop comprising:
 a clock terminal coupled to a clock source and configured to receive a clock signal; 
 an input terminal configured to receive second data; and 
 an output terminal configured to output first data according to the second data and the clock signal; and 
 
 the reset circuit further comprises a logic circuit configured to offset the first data by a fixed value so as to update the second data, the logic circuit comprising:
 an input terminal coupled to the output terminal of the flip flop and configured to receive the first data; 
 a first output terminal coupled to the input terminal of the flip flop and configured to output the second data; and 
 a second output terminal coupled to the output terminal of the reset circuit and configured to perform the reset operation when the first data has not yet reached a constant or configured to stop performing the reset operation when the first data has reached the constant, the constant corresponding to the first predetermined time interval. 
 
 
     
     
       6. A control circuit, comprising:
 a reset circuit coupled to a digital circuit of a functional circuit and configured to perform a reset operation to the digital circuit; and 
 a determination circuit coupled to the reset circuit and configured to determine whether a first predetermined time interval has elapsed so as to control the reset circuit to stop performing the reset operation when the first predetermined time interval has elapsed; 
 wherein the functional circuit further comprises an analog circuit, the digital circuit is coupled to the analog circuit, and the first predetermined time interval corresponds to a time required for the analog circuit to stabilize; 
 the determination circuit determines whether the first predetermined time interval has elapsed by counting; 
 the functional circuit further comprises an oscillation source; 
 the control circuit further comprises:
 an operation voltage generation circuit, comprising:
 an output terminal coupled to the analog circuit; and 
 
 a first capacitor, comprising:
 a first terminal coupled to the output terminal of the operation voltage generation circuit; and 
 a second terminal coupled to the oscillation source; 
 
 
 the reset circuit comprises:
 an output terminal configured to perform the reset operation or stop the reset operation; and 
 the first predetermined time interval corresponds to the time required for a voltage of the first terminal of the first capacitor to reach a ratio of a predetermined voltage; and 
 
 the operation voltage generation circuit further comprises a bias voltage generator configured to provide a bias voltage to charge the first capacitor.