Processor with variable rate execution unit

Abstract

A processor has functional units that fetch and decode architectural instructions of an architectural instruction set at a first rate, a register that stores a value of an indicator programmable by execution of an architectural instruction of the architectural instruction set, and an execution unit. The execution unit includes a first memory that holds data, a second memory that holds instructions of a program, and a plurality of processing units that execute the program instructions at a second rate to perform operations on data received from the first memory to generate results to be written to the first memory. The instructions are of an instruction set that is distinct from the architectural instruction set. The second rate is the first rate when the indicator is programmed with a first value and the second rate is less than the first rate when the indicator is programmed with a second value.

The invention claimed is: 
     
       1. A processor, comprising:
 a plurality of functional units that fetch and decode architectural instructions of an architectural instruction set of the processor at a first rate; 
 a register that stores a value of an indicator, the value is programmable by execution of an architectural instruction of the architectural instruction set; and 
 an execution unit, comprising: 
 a first memory that holds data; 
 a second memory that holds non-architectural instructions of a program, the non-architectural instructions are of an instruction set that is distinct from the architectural instruction set; 
 a plurality of processing units that execute the non-architectural instructions at a second rate to perform operations on data received from the first memory to generate results to be written to the first memory; and 
 the second rate is the first rate when the indicator is programmed with a first predetermined value and the second rate is less than the first rate when the indicator is programmed with a second predetermined value. 
 
     
     
       2. The processor of  claim 1 , further comprising:
 architectural media registers accessible by architectural instructions of the architectural instruction set; 
 a buffer; 
 the processor is configured to transfer data between the architectural media registers and the buffer at the first rate in response to execution of an architectural instruction of the architectural instruction set; and 
 the processor is configured to transfer data between the buffer and the first memory at the second rate in response to execution of the non-architectural instructions of the program. 
 
     
     
       3. The processor of  claim 2 , further comprising:
 the first memory is single-ported and is accessible in an arbitrated fashion by the buffer and the plurality of processing units. 
 
     
     
       4. The processor of  claim 2 , further comprising:
 the first memory dual-ported and is accessible in a concurrent fashion by the buffer and the plurality of processing units. 
 
     
     
       5. The processor of  claim 1 , further comprising:
 clock generation logic that generates a first clock signal that has the first rate at which the plurality of functional units fetch and decode the architectural instructions; and 
 clock reduction logic that receives the value of the indicator and that receives the first clock signal and in response generates a second clock signal that has the second rate, based on the value of the indicator, at which the plurality of processing units execute the non-architectural program instructions. 
 
     
     
       6. The processor of  claim 5 , further comprising:
 each processing unit of the plurality of processing units comprises a plurality of pipeline staging registers each configured to receive the second clock signal. 
 
     
     
       7. The processor of  claim 5 , further comprising:
 the clock reduction logic generates the second clock signal by gating the first clock signal based on the value of the indicator. 
 
     
     
       8. The processor of  claim 5 , further comprising:
 the clock reduction logic comprises a clock divider circuit that divides the first clock signal to generate the second clock signal by a divisor specified in the value of the indicator. 
 
     
     
       9. The processor of  claim 1 , further comprising:
 the value of the indicator is programmable to a plurality of different predetermined second values, and when the indicator is programmed with each predetermined second value of the plurality of different predetermined second values the second rate is a corresponding different rate less than the first rate. 
 
     
     
       10. The processor of  claim 1 , further comprising:
 the second memory is writable with the non-architectural instructions of the program by execution of an architectural instruction of the architectural instruction set. 
 
     
     
       11. The processor of  claim 1 , further comprising:
 the plurality of processing units are configured to start execution of the program in response to execution of an architectural instruction of the architectural instruction set. 
 
     
     
       12. The processor of  claim 1 , further comprising:
 a sequencer that fetches the non-architectural program instructions from the second memory and decodes them to generate control words that control the plurality of processing units to execute the non-architectural program instructions at the second rate. 
 
     
     
       13. The processor of  claim 1 , further comprising:
 the plurality of processing units are configured to perform arithmetic operations on the data received from the first memory to accumulate first results and to perform activation functions on the first results to generate second results to be written to the first memory. 
 
     
     
       14. The processor of  claim 13 , further comprising:
 the execution unit further comprises a third memory that holds weights; and 
 the plurality of processing units execute the non-architectural program instructions at the second rate to perform operations on data received from the first memory and on weights received from the third memory to generate results to be written to the first memory. 
 
     
     
       15. The processor of  claim 13 , further comprising:
 the plurality of processing units execute the non-architectural program instructions at the second rate to perform convolution operations associated with neural networks. 
 
     
     
       16. The processor of  claim 13 , further comprising:
 the plurality of processing units execute the non-architectural program instructions at the second rate to perform pooling operations associated with neural networks. 
 
     
     
       17. A method of operating a processor having an execution unit that includes a first memory that holds data, a second memory that holds non-architectural instructions of a program, and a plurality of processing units, the method comprising:
 fetching and decoding, by a plurality of functional units of a processor, architectural instructions of an architectural instruction set of the processor at a first rate; 
 programming into a register a value of an indicator, the value is programmable by execution of an architectural instruction of the architectural instruction set; 
 executing, by the plurality of processing units, the non-architectural program instructions at a second rate to perform operations on data received from the first memory to generate results to be written to the first memory; 
 the non-architectural instructions are of an instruction set that is distinct from the architectural instruction set; and 
 the second rate is the first rate when the indicator is programmed with a first predetermined value and the second rate is less than the first rate when the indicator is programmed with a second predetermined value. 
 
     
     
       18. The method of  claim 17 , further comprising:
 the processor further includes architectural media registers accessible by architectural instructions of the architectural instruction set and a buffer; 
 transferring, by the execution unit, data between the architectural media registers and the buffer at the first rate in response to execution of an architectural instruction of the architectural instruction set; and 
 transferring, by the execution unit, data between the buffer and the first memory at the second rate in response to execution of non-architectural instructions of the program. 
 
     
     
       19. The method of  claim 17 , further comprising:
 generating a first clock signal that has the first rate at which the plurality of functional units fetch and decode the architectural instructions; and 
 receiving the value of the indicator and receiving the first clock signal and in response generating a second clock signal that has the second rate, based on the value of the indicator, at which the plurality of processing units execute the non-architectural program instructions. 
 
     
     
       20. The method of  claim 17 , further comprising:
 starting, by the execution unit, execution of the program in response to execution of an architectural instruction of the architectural instruction set. 
 
     
     
       21. The method of  claim 17 , further comprising:
 fetching the non-architectural program instructions from the second memory and decoding them to generate control words that control the plurality of processing units to execute the non-architectural program instructions at the second rate. 
 
     
     
       22. The method of  claim 17 , further comprising:
 performing, by the plurality of processing units, arithmetic operations on the data received from the first memory to accumulate first results; 
 performing activation functions on the first results to generate second results; and 
 writing the second results to the first memory. 
 
     
     
       23. A computer program product encoded in at least one non-transitory computer usable medium for use with a computing device, the computer program product comprising:
 computer usable program code embodied in said medium, for specifying a processor, the computer usable program code comprising: 
 first program code for specifying a plurality of functional units that fetch and decode architectural instructions of an architectural instruction set of the processor at a first rate; 
 second program code for specifying a register that stores a value of an indicator, the value is programmable by execution of an architectural instruction of the architectural instruction set; and 
 third program code for specifying an execution unit, comprising: 
 a first memory that holds data; 
 a second memory that holds non-architectural instructions of a program, the non-architectural instructions are of an instruction set that is distinct from the architectural instruction set; 
 a plurality of processing units that execute the non-architectural program instructions at a second rate to perform operations on data received from the first memory to generate results to be written to the first memory; and 
 the second rate is the first rate when the indicator is programmed with a first predetermined value and the second rate is less than the first rate when the indicator is programmed with a second predetermined value.