Wireless circuitry with scalable accuracy

Abstract

Described herein are architectures, platforms and methods for implementing scalable power in a wireless device. Multiple radio access technology architectures running different operating clock frequencies are supported by providing a scaled static clock frequency and dynamic clock frequencies by dynamically switching parallel paths of processing resources.

What is claimed is: 
     
       1. A method of adjusting clock frequency in a transmitting or receiving device comprising:
 determining a particular accuracy of transmitting or receiving by the device; 
 allocating one or more parallel processing resources to adjust for the particular accuracy; and 
 dynamically switching one or more parallel paths on or off to respectively connect the one or more parallel processing resources to process data signals based on the particular accuracy, the data signals being indicative of at least one quantization step, and the dynamic switching of the one or more parallel paths being related to the at least one quantization step. 
 
     
     
       2. The method of  claim 1 , wherein the adjusting clock frequency is based on a static clock. 
     
     
       3. The method of  claim 2 , further comprises:
 determining a lower bandwidth of operation for the device to generate a lower static frequency for the static clock, and determining a higher bandwidth operation for the device to generate a higher static frequency for the static clock. 
 
     
     
       4. The method of  claim 1 , wherein the adjusting clock frequency is based on a dynamic clock. 
     
     
       5. The method of  claim 1 , wherein the allocating one or more parallel processing resources is based on a received data signal. 
     
     
       6. The method of  claim 1 , wherein determining the particular accuracy is based on one or more of the following:
 bandwidth of a received data signal; 
 end and beginning of bandwidth of the data signal; 
 gap between several bandwidth allocations needed by the data signal; 
 output power of the device; 
 band used to transmit from the device; and 
 data signal values. 
 
     
     
       7. A modem device comprising:
 an interface configured to receive a data signal from a radio access technology; 
 a scaled static clock configured to support the radio access technology; and 
 a plurality of parallel paths for processing resources that are dynamically switched on or off to generate a particular clock frequency supporting the radio access technology, the received data signal being indicative of at least one quantization step, and the dynamic switching of the plurality of parallel paths being related to the at least one quantization step. 
 
     
     
       8. The device of  claim 7 , wherein the received data signal determines an accuracy. 
     
     
       9. The device of  claim 8 , wherein the accuracy is related to the particular clock frequency provided by the parallel paths that are dynamically switched on or off. 
     
     
       10. The device of  claim 7 , wherein the scaled static clock is configured from a lower bandwidth operation at a lower static frequency and higher bandwidth operation at a higher static frequency. 
     
     
       11. The device of  claim 7 , wherein accuracy is related to number of physical resource blocks that are allocated to support communication for the radio access technology. 
     
     
       12. The device of  claim 7 , wherein accuracy is related to one or more of the following: bandwidth of the data signal; end and beginning of resource block; output of the device; band used to transmit; gap between resource block allocations and data signal values. 
     
     
       13. The device of  claim 7 , wherein the plurality of parallel paths for processing resources are configured to perform digital operations on the received data signal. 
     
     
       14. A wireless device comprising:
 one or more processors; 
 memory coupled to the processors, wherein the memory comprises one or more lookup tables; 
 a modem coupled to the processors and memory, wherein the memory comprising a scaled static clock and parallel paths of resources that are dynamically switched on and off to provide particular operating frequencies to support multiple radio access technologies located on the wireless device, 
 wherein received data signals determine quantization steps, and 
 wherein the parallel paths of the resources that are dynamically switched on and off are related to the quantization steps. 
 
     
     
       15. The wireless device of  claim 14 , wherein the lookup tables determine which radio access technologies, band requirements, operating frequencies and which parallel paths of resources to switch on. 
     
     
       16. The wireless device of  claim 15 , wherein band requirements include lower frequency and upper frequency of received data signals. 
     
     
       17. The wireless device of  claim 14 , wherein the lookup tables relate an accuracy with one or more of the following: bandwidth of a data signal; end and beginning of bandwidth of the data signal; gap between several bandwidth allocations needed by the data signal; output power of the wireless device; band frequency used to transmit; and data signal values. 
     
     
       18. The wireless device of  claim 14 , wherein the parallel paths of resources that are dynamically switched on and off to provide particular operating frequencies are related to a dynamic clock. 
     
     
       19. The wireless device of  claim 14 , wherein the parallel paths of resources that are dynamically switched on and off are related to received data signals.