Semiconductor device

Abstract

To provide an asynchronous circuit capable of power gating, a semiconductor device is configured with first to third terminals, a latch circuit, and a memory circuit. The third terminal outputs “false” when “false” is input to the first terminal and the second terminal. The third terminal outputs “true” when “true” is input to the first terminal and the second terminal. The third terminal outputs a truth value that is the same as the previous output, when “true” is input to one of the first terminal and the second terminal and “false” is input to the other of the first terminal and the second terminal. The memory circuit is capable of storing data stored in the latch circuit, while supply of a power supply voltage is stopped. The memory circuit includes a transistor that contains a metal oxide in a channel formation region.

The invention claimed is: 
     
       1. A semiconductor device comprising:
 a Muller C-element comprising:
 a latch circuit; and 
 a first memory element comprising:
 a first transistor comprising an oxide semiconductor in a channel formation region; 
 a second transistor; and 
 a first capacitor, 
 
 
 wherein one of a source and a drain of the first transistor is electrically connected to the first capacitor and a gate of the second transistor, and 
 wherein the other of the source and the drain of the first transistor and on of a source and a drain of the second transistor are electrically connected to the latch circuit. 
 
     
     
       2. The semiconductor device according to  claim 1 , wherein the Muller C-element has a plurality of input terminals. 
     
     
       3. The semiconductor device according to  claim 1 , wherein the Muller C-element has two or three input terminals. 
     
     
       4. The semiconductor device according to  claim 1 ,
 wherein the Muller C-element further comprises a second memory element, 
 wherein the second memory element comprises:
 a third transistor comprising an oxide semiconductor in a channel formation region; 
 a fourth transistor; and 
 a second capacitor, 
 
 wherein the latch circuit comprises:
 a first inverter comprising a first input terminal and a first output terminal; and 
 a second inverter comprising a second input terminal and a second output terminal, 
 
 wherein the first input terminal is electrically connected to the second output terminal, 
 wherein the first output terminal is electrically connected to the second input terminal, 
 wherein the first output terminal is electrically connected to the first capacitor through the first transistor, and 
 wherein the second output terminal is electrically connected to the second capacitor through the third transistor.