Thermal stress compensation bonding layers and power electronics assemblies incorporating the same

Abstract

A thermal stress compensation layer includes a metal inverse opal (MIO) layer with a plurality of hollow spheres and a predefined porosity disposed between a pair of bonding layers. The thermal stress compensation layer has a melting point above a TLP sintering temperature and the pair of bonding layers each have a melting point below the TLP sintering temperature such that the MIO layer can be transient liquid phase bonded between a metal substrate and a semiconductor device. The pair of bonding layers may comprise a first pair of bonding layers and a second pair of bonding layers with the first pair of bonding layers disposed between the MIO layer and the second pair of bonding layers. The first pair of bonding layers may have a melting point above the TLP sintering temperature and the second pair of bonding layers may have a melting point below the TLP sintering temperature.

What is claimed is: 
     
       1. A transient liquid phase (TLP) bonding layer comprising:
 a thermal stress compensation layer disposed between at least one pair of bonding layers, the thermal stress compensation layer comprising a metal inverse opal (MIO) layer with a plurality of hollow spheres and a predefined porosity, wherein the MIO layer comprises a first surface, a second surface and a graded porosity between the first surface and the second surface; 
 wherein the thermal stress compensation layer has a melting point above a TLP sintering temperature and the at least one pair of bonding layers each have a melting point below the TLP sintering temperature. 
 
     
     
       2. The TLP bonding layer of  claim 1 , wherein the MIO layer comprises a graded stiffness between the first surface and the second surface. 
     
     
       3. The TLP bonding layer of  claim 1 , wherein:
 the at least one pair of bonding layers comprise a first pair of bonding layers and a second pair of bonding layers, wherein: 
 the first pair of bonding layers are disposed between the MIO layer and the second pair of bonding layers; 
 each of the first pair of bonding layers have a melting point above the TLP sintering temperature; and 
 each of the second pair of bonding layers have a melting point below the TLP sintering temperature. 
 
     
     
       4. The TLP bonding layer of  claim 3 , wherein the MIO layer is a copper inverse opal (CIO) layer, the first pair of bonding layers are formed from nickel, silver or alloys thereof, and the second pair of bonding layers are formed from tin, indium or alloys thereof. 
     
     
       5. The TLP bonding layer of  claim 1 , wherein the MIO layer has a thickness between about 50 microns and about 150 microns. 
     
     
       6. The TLP bonding layer of  claim 1 , wherein the plurality of hollow spheres have an average diameter between about 5 μm and about 50 μm. 
     
     
       7. The TLP bonding layer of  claim 1 , wherein the pair of bonding layers each have a thickness between about 2 microns and about 10 microns. 
     
     
       8. A power electronics assembly comprising:
 a metal substrate; 
 a semiconductor device; 
 a thermal stress compensation layer disposed between at least one pair of bonding layers disposed between and bonded to the semiconductor device and the metal substrate, the thermal stress compensation layer comprising a metal inverse opal (MIO) layer with a plurality of hollow spheres and a predefined porosity, wherein the MIO layer comprises a first surface, a second surface and a graded porosity between the first surface and the second surface; and 
 wherein the thermal stress compensation layer has a melting point above a TLP sintering temperature and the at least one pair of bonding layers each have a melting point below the TLP sintering temperature. 
 
     
     
       9. The power electronics assembly of  claim 8 , wherein the MIO layer comprises a graded stiffness between the first surface and the second surface. 
     
     
       10. The power electronics assembly of  claim 8 , wherein the plurality of hollow spheres have an average diameter between about 5 μm and about 50 μm. 
     
     
       11. The power electronics assembly of  claim 8 , further comprising a pair of bond layers, wherein:
 the MIO layer is disposed between the pair of bond layers and transient liquid phase (TLP) bonded to the metal substrate and the semiconductor device through the at least one pair of bonding layers; and 
 each of the pair of bond layers have a melting point above a TLP sintering temperature. 
 
     
     
       12. The power electronics assembly of  claim 8 , wherein the MIO layer is electroplate bonded or electroless plate bonded to the metal substrate and the semiconductor device. 
     
     
       13. A process for manufacturing a power electronics assembly comprising:
 positioning a thermal stress compensation layer disposed between at least one pair of bonding layers between a metal substrate and a semiconductor device to provide a metal substrate/semiconductor device assembly, the thermal stress compensation layer comprising a metal inverse opal (MIO) layer with a plurality of hollow spheres and a predefined porosity, wherein the MIO layer comprises a first surface, a second surface and a graded porosity between the first surface and the second surface;
 wherein the thermal stress compensation layer has a melting point above a TLP sintering temperature and the at least one pair of bonding layers each have a melting point below the TLP sintering temperature; and 
 
 bonding the MIO layer to the metal substrate and the semiconductor device. 
 
     
     
       14. The process of  claim 13 , further comprising:
 heating the metal substrate/semiconductor device assembly to a transient liquid phase (TLP) sintering temperature between about 280° C. and 350° C., wherein the at least one pair of bonding layers each have a melting point less than the TLP sintering temperature, and the MIO layer has a melting point greater than the TLP sintering temperature such that the at least one pair of bonding layers at least partially melt and form a TLP bond between the MIO layer and the metal substrate and between the MIO layer and the semiconductor device; and 
 cooling the power electronics assembly from the TLP sintering temperature, wherein the thermal compensation layer compensates for thermal contraction mismatch between the semiconductor device and the metal substrate during cooling from the TLP sintering temperature to ambient temperature. 
 
     
     
       15. The process of  claim 14 , wherein:
 the at least one pair of bonding layers comprise a first pair of bonding layers and a second pair of bonding layers: 
 the first pair of bonding layers are disposed between the MIO layer and the second pair of bonding layers; 
 each of the first pair of bonding layers have a melting point above the TLP sintering temperature; and 
 each of the second pair of bonding layers have a melting point below the TLP sintering temperature. 
 
     
     
       16. The process of  claim 13 , further comprising placing the metal substrate/semiconductor device assembly in an electroplating bath or an electroless plating bath and electroplate bonding or electroless plate bonding the MIO layer to the metal substrate and the semiconductor device. 
     
     
       17. The process of  claim 13 , wherein the MIO layer comprises a graded stiffness between the first surface and the second surface.