Semiconductor device

Abstract

The present invention provides a semiconductor device, including a substrate, two gate structures disposed on a channel region of the substrate, an epitaxial layer disposed in the substrate between two gate structures, a first dislocation disposed in the epitaxial layer, wherein the profile of the first dislocation has at least two non-parallel slanting lines, and a second dislocation disposed adjacent to a top surface of the epitaxial layer, and the profile of the second dislocation has at least two non-parallel slanting lines.

What is claimed is: 
     
       1. A semiconductor device, comprising:
 a substrate; 
 two gate structures disposed on the substrate; 
 an epitaxial layer disposed in the substrate between two gate structures; 
 a second dislocation disposed adjacent to a top surface of the epitaxial layer, and the profile of the second dislocation has at least two non-parallel slanting lines, and the two non-parallel slanting lines compose a V profile; 
 a first dislocation disposed in the epitaxial layer, wherein the profile of the first dislocation has at least two non-parallel slanting lines, and the two non-parallel slanting lines compose a reverse V profile, and wherein the first dislocation does not contact a top surface of the epitaxial layer directly, and an intersection point of the at least two non-parallel slanting lines of the first dislocation is disposed in the epitaxial layer, wherein the intersection point is disposed below the top surface of the epitaxial layer; and 
 a contact structure directly contacts the top surface of the epitaxial layer, wherein part of the contact structure is disposed lower than a top surface of the substrate. 
 
     
     
       2. The semiconductor device of  claim 1 , wherein the contact structure comprises silicide. 
     
     
       3. The semiconductor device of  claim 1 , wherein the contact structure has a bottommost surface with a V-shaped profile. 
     
     
       4. The semiconductor device of  claim 3 , wherein the bottommost surface of the contact structure directly contact with the second dislocation. 
     
     
       5. The semiconductor device of  claim 1 , wherein the gate structure is a gate structure of an n-type metal-oxide-silicon (NMOS) field-effect transistor (FET). 
     
     
       6. The semiconductor device of  claim 1 , wherein the material of the epitaxial layer includes SiC, SiP, or SiCP. 
     
     
       7. The semiconductor device of  claim 1 , further comprising two spacers each respectively disposed on two sides of each gate structure, wherein the second dislocation contacts the spacer directly. 
     
     
       8. A semiconductor device, comprising:
 a substrate; 
 two gate structures disposed on the substrate; 
 an epitaxial layer disposed in the substrate between two gate structures, wherein a bottom portion of the epitaxial layer is larger than a top portion thereof; 
 a second dislocation disposed adjacent to a top surface of the epitaxial layer, and the profile of the second dislocation has at least two non-parallel slanting lines, and the two non-parallel slanting lines compose a V profile, and an intersection point of the at least two non-parallel slanting lines of the second dislocation is disposed in the epitaxial layer, wherein the intersection point is disposed below the top surface of the epitaxial layer; and 
 a contact structure directly contacts the top surface of the epitaxial layer, wherein part of the contact structure is disposed lower than a top surface of the substrate. 
 
     
     
       9. The semiconductor device of  claim 8 , wherein the contact structure comprises silicide. 
     
     
       10. The semiconductor device of  claim 8 , wherein the contact structure has a bottommost surface with a V-shaped profile. 
     
     
       11. The semiconductor device of  claim 10 , wherein the bottommost surface of the contact structure directly contact with the second dislocation. 
     
     
       12. The semiconductor device of  claim 8 , wherein the gate structure is a gate structure of an n-type metal-oxide-silicon (NMOS) field-effect transistor (FET). 
     
     
       13. The semiconductor device of  claim 8 , wherein the material of the epitaxial layer includes SiC, SiP, or SiCP. 
     
     
       14. The semiconductor device of  claim 8 , further comprising two spacers each respectively disposed on two sides of each gate structure, wherein the second dislocation contacts the spacer directly.