Switched interface stacked-die memory architecture

Abstract

Systems and methods disclosed herein include those that may receive a memory request including a requested memory address and may send the memory request directly to an address decoder associated with a stacked-die memory vault without knowing whether a repair address is required. If a subsequent analysis of the memory request shows that a repair address is required, an in-process decode of the requested memory address can be halted and decoding of the repair address initiated.

What is claimed is: 
     
       1. A system, comprising:
 a memory vault comprising a stacked plurality of memory arrays, each memory array of the stacked plurality of memory arrays located on a memory die of a plurality of stacked memory dies; 
 a memory vault controller (MVC) communicatively coupled to the memory vault, the MVC comprising a memory vault repair logic (MVRL), the MVRL to receive a memory request including a requested memory address, the MVRL including at least one lookup table to translate the requested memory address into a repair address, and the MVRL to send one or both of the memory request and the repair address to the memory vault; and 
 a host processor communicatively coupled to the MVC. 
 
     
     
       2. The system of  claim 1 , wherein the MVC comprises a repair decode assessment module to estimate a latency associated with translating the requested memory address into the repair address. 
     
     
       3. The system of  claim 1 , wherein the MVC comprises a variable latency decision module (VLDM) coupled to the repair decode assessment module, the VLDM to cause the memory request including the requested memory address to be passed to a memory address decoder associated with a selected memory vault if the estimated latency is greater than a selected amount. 
     
     
       4. The system of  claim 1 , wherein the memory vault comprises a spare memory die. 
     
     
       5. The system of  claim 1 , wherein the MVC comprises a spare memory array. 
     
     
       6. The system of  claim 5 , wherein the spare memory array comprises one or both of a static random-access memory (SRAM) and a dynamic random-access memory (DRAM). 
     
     
       7. The system of  claim 1 , wherein the MVC is configured to provide memory sequencing operations. 
     
     
       8. The system of  claim 1 , wherein the MVC is configured to provide data buffering operations. 
     
     
       9. The system of  claim 1 , wherein the MVC is configured to provide memory array repair operations. 
     
     
       10. A system, comprising:
 a memory vault comprising a stacked plurality of memory arrays, each memory array of the stacked plurality of memory arrays located on a memory die of a plurality of stacked memory dies; 
 a memory vault controller (MVC) communicatively coupled to the memory vault, the MVC comprising a memory vault repair logic (MVRL), the MVRL to receive a memory request including a requested memory address and to send one or both the memory request and a modified memory request to the memory vault, the modified memory request to include a repair address, the MVRL comprising a partial address decoder to partially decode the requested memory address, a repair address lookup table communicatively coupled to the partial address decoder to translate the requested memory address into the repair address, and a bad block logic coupled to the partial address decoder to select the repair address lookup table from a plurality of repair address lookup tables; and 
 a host processor communicatively coupled to the MVC. 
 
     
     
       11. The system of  claim 10 , wherein the plurality of repair address lookup tables comprises a direct-mapped table. 
     
     
       12. The system of  claim 10 , wherein the plurality of repair address lookup tables comprises a fully associative tag random-access memory. 
     
     
       13. The system of  claim 10 , wherein the plurality of repair address lookup tables comprises a set associative tag random-access memory. 
     
     
       14. The system of  claim 10 , wherein the MVRL comprises a repair decode assessment module coupled to the partial address decoder to estimate a latency associated with translating the requested memory address into the repair address. 
     
     
       15. The system of  claim 10 , wherein MVRL comprises an arithmetic/logic unit (ALU) coupled to the repair address lookup table to calculate the repair address using an address offset stored in the repair address lookup table as an entry associated with the requested memory address. 
     
     
       16. A system comprising:
 a memory vault; 
 a memory vault controller (MVC) communicatively coupled to the memory vault, the MVC comprising:
 a memory vault repair logic (MVRL), the MVRL to receive a memory request including a requested memory address, and the MVRL to send one or both of the memory request and a repair address to the memory vault; 
 a partial address decoder to partially decode the requested memory address; 
 a repair address lookup table communicatively coupled to the partial address decoder to translate the requested memory address into the repair address; 
 a logic block coupled to the partial address decoder to select the repair address lookup table from a plurality of repair address lookup tables; and 
 a feedback loop operable to determine whether the requested memory address references a non-defective memory location; and 
 
 a host processor communicatively coupled to the MVC. 
 
     
     
       17. The system of  claim 16 , wherein the bad block logic is configured to select the repair address lookup table based upon a number of bad blocks. 
     
     
       18. The system of  claim 16 , wherein the bad block logic is configured to select the repair address lookup table based upon a number of words in a bad block as determined by the partial address decoder. 
     
     
       19. The system of  claim 16 , wherein the MVRL further comprises an address bus gating logic coupled to pass the requested memory address to one or both of a memory address decoder and the partial address decoder. 
     
     
       20. The system of  claim 19 , wherein the memory address decoder comprises an address selector to reject a partially decoded requested memory address and to initiate decoding of the repair address if the requested memory address is determined to reference at least one defective memory cell. 
     
     
       21. A computer-readable medium having a program to cause a computer-based system to:
 receive, at a memory vault repair logic (MVRL) of a memory vault controller (MVC), a memory request including a requested memory address; 
 translate the requested memory address into a repair address; and 
 send one or both of the memory request and the repair address to a memory vault communicatively coupled to the MVC, wherein the memory vault includes a stacked plurality of memory arrays, each memory array of the stacked plurality of memory arrays located on a memory die of a plurality of stacked memory dies. 
 
     
     
       22. The computer-readable medium of  claim 21 , further to cause the computer-based system to:
 estimate a latency associated with translating the requested memory address into the repair address at the MVC, cause the memory request including the requested memory address to be passed to a memory address decoder if the estimated latency is greater than a selected amount, perform memory sequencing operations at the MVC, perform data buffering operations at the MVC, or perform memory array repair operations at the MVC. 
 
     
     
       23. A computer-readable medium having a program to cause a computer-based system to:
 receive, at a memory vault repair logic (MVRL) of a memory vault controller (MVC), a memory request including a requested memory address; 
 send one or both the memory request and a modified memory request from the MVRL to a memory vault communicatively coupled to the MVC, the modified memory request including a repair address; 
 partially decode, at the MVRL, the requested memory address; 
 translate, using a repair address lookup table of the MVRL, the requested memory address into the repair address; and 
 select, at the MVRL, the repair address lookup table from a plurality of repair address lookup tables. 
 
     
     
       24. The computer-readable medium of  claim 23 , further to cause the computer-based system to:
 estimate, at the MVRL, a latency associated with translating the requested memory address into the repair address, or calculate, at the MVRL, the repair address using an address offset stored in the repair address lookup table as an entry associated with the requested memory address. 
 
     
     
       25. A computer-readable medium having a program to cause a computer-based system to:
 receive, at a memory vault repair logic (MVRL) of a memory vault controller (MVC), a memory request including a requested memory address; 
 send one or both of the memory request and the repair address to a memory vault communicatively coupled to the MVC; 
 partially decode, at the MVC, the requested memory address; 
 translate, using a repair address lookup table at the MVC, the requested memory address into the repair address; 
 select, at the MVC, the repair address lookup table from a plurality of repair address lookup tables; and 
 determine, at the MVC, whether the requested memory address references a non-defective memory location. 
 
     
     
       26. The computer-readable medium of  claim 25 , further cause the computer-based system to:
 select, at the MVC, the repair address lookup table based upon a number of bad blocks, select, at the MVC, the repair address lookup table based upon a number of words in a bad block as determined by the MVC, pass the requested memory address from an address bus gating logic of the MVC to one or both of a memory address decoder of the MVC and a partial address decoder of the MVC, reject, at the memory address decoder, a partially decoded requested memory address, or initiate, at the memory address decoder, a decoding of the repair address if the requested memory address is determined to reference at least one defective memory cell.