Thin film transistor and method of fabricating the same, array substrate and display apparatus

Abstract

A method of fabricating a TFT includes a step of forming a gate electrode, a gate insulation layer, an active layer, a source electrode, a drain electrode, a passivation layer and a connection electrode, wherein a pattern including the gate electrode, the source electrode and the drain electrode, the active layer and the gale insulation layer is formed by one patterning process, a pattern including the passivation layer and a via hole through the passivation layer is formed by one patterning process, and a pattern of the connection electrode is formed by one patterning process to electrically connect the source electrode and the drain electrode with the active layer.

What is claimed is: 
     
       1. A method of fabricating a thin film transistor comprising a substrate, a gate electrode, a gate insulation layer, an active layer, a source electrode, a drain electrode, a passivation layer and a connection electrode, the method comprising:
 forming a first conductive film layer, a gate insulation film layer and an active film layer on the substrate; 
 patterning the first conductive film layer, the active film layer and the gate insulation film layer by one patterning process to form a pattern of the gate electrode, the source electrode and the drain electrode, a pattern of the active layer, and a pattern of the gate insulation layer, respectively; 
 forming a passivation film layer on a side of the gate electrode, the source electrode, the drain electrode, the active layer and the gate insulation layer distal to the substrate; 
 patterning the passivation film layer by one patterning process to form a pattern comprising the passivation layer and a via hole through the passivation layer; 
 forming a second conductive film layer on a side of the passivation layer distal to the substrate; and 
 patterning the second conductive film layer by one patterning process to form a pattern of the connection electrode, the connection electrode being configured to electrically connect the source electrode and the drain electrode to the active layer, respectively, 
 wherein the first conductive film layer, the gate insulation film layer and the active film layer are formed on the substrate sequentially in a direction away from the substrate. 
 
     
     
       2. The method according to  claim 1 , wherein the step of forming the patterns of the gate electrode, the source electrode, the drain electrode, the active layer and the gate insulation layer by one patterning process further comprises:
 forming the pattern of the gate electrode, the source electrode and the drain electrode by performing an exposure process and an etching process one time; and 
 forming the patterns of the gate insulation layer and the active layer by an ashing process and an etching process, such that the source electrode and the drain electrode are at least partially exposed. 
 
     
     
       3. The method according to  claim 2 , wherein the exposure process is performed by using a halftone mask which comprises a blocking region for blocking ultraviolet light, a partial transmissive region for allowing the ultraviolet light to partially transmit therethrough, and a transmissive region for allowing the ultraviolet light to completely transmit therethrough; an orthographic projection of each of the gate insulation layer and the active layer completely overlaps with that of the blocking region, an orthographic projection of a portion of each of the source electrode and the drain electrode not covered by the gate insulation layer and the active layer completely overlaps with an orthographic projection of the partial transmissive region, and an orthographic projection of gaps between the source electrode, the drain electrode and the gate electrode completely overlaps with that of the transmissive region. 
     
     
       4. The method according to  claim 2 , wherein during the ashing process and the etching process, the patterns of the active layer and the gate insulation layer are formed on the gate electrode, the drain electrode and the source electrode, and
 an area of an orthographic projection of each of the gate insulation layer and the active layer on the source electrode is less than that of an orthographic projection of the source electrode, and an area of an orthographic projection of each of the gate insulation layer and the active layer on the drain electrode is less than that of an orthographic projection of the drain electrode. 
 
     
     
       5. The method according to  claim 2 , wherein during the ashing process and the etching process, the patterns of the gate insulation layer and the active layer are formed only on the gate electrode. 
     
     
       6. The method according to  claim 2 , wherein the exposure process is a process of double-slit diffraction. 
     
     
       7. The method according to  claim 1 , wherein the step of forming the pattern comprising the passivation layer and the via hole through the passivation layer comprises:
 forming a first via hole and a second via hole through the passivation layer to expose portions of a first region of the active layer, respectively, the first region of the active layer being stacked with the gate insulation layer and the gate electrode, and an orthographic projection of at least a portion of the first region of the active layer overlapping with that of the gate electrode; and 
 forming a third via hole through the passivation layer to expose a portion of the source electrode, and forming a fourth via hole through the passivation layer to expose a portion of the drain electrode, 
 wherein the connection electrode is formed to electrically connect the source electrode and the active layer via the first via hole and third via hole and electrically connect the drain electrode and the active layer via the second via hole and fourth via hole. 
 
     
     
       8. The method according to  claim 1 , wherein the active layer is formed of a metal oxide.