Method and structure for forming FinFET CMOS with dual doped STI regions

Abstract

A method of making a semiconductor device includes forming a first fin of a first transistor in a substrate; forming a second fin of a second transistor in the substrate; disposing a first doped oxide layer including a first dopant onto the first fin and the second fin, the first dopant being an n-type dopant or a p-type dopant; disposing a mask over the first fin and removing the first doped oxide layer from the second fin; removing the mask and disposing a second doped oxide layer onto the first doped oxide layer over the first doped oxide layer covering the first fin and directly onto the second fin, the second doped oxide layer including an n-type dopant or a p-type dopant that is different than the first dopant; and annealing to drive in the first dopant into a portion of the first fin and the second dopant into a portion of the second fin.

What is claimed is: 
     
       1. A method of making a semiconductor device, the method comprising:
 forming a first fin of a first transistor in a substrate; 
 forming a second fin of a second transistor in the substrate; 
 disposing a first doped oxide layer comprising a first dopant onto the first fin and the second fin, the first dopant being an n-type dopant or a p-type dopant; 
 disposing a mask over the first fin and removing the first doped oxide layer from the second fin; 
 removing the mask and disposing a second doped oxide layer onto the first doped oxide layer over the first fin and directly onto the second fin, the second doped oxide layer comprising an n-type dopant or a p-type dopant that is different than the first dopant; 
 etching to recess the first doped oxide layer and the second doped oxide layer, leaving a layer of the first doped oxide layer on the first fin as a first doped oxide spacer and a layer of the second doped oxide layer on the second fin as a second doped oxide spacer; 
 annealing, after etching to recess, by a thermal process and under conditions sufficient to drive in the first dopant into a portion of the first fin and the second dopant into a portion of the second fin, and to drive the first dopant into the substrate beneath the first fin and the second dopant into the substrate beneath the second fin; 
 removing the first doped oxide spacer from the first fin and the second doped oxide spacer from the second fin; 
 depositing an oxide between the first fin and the second fin; and 
 forming a first gate on the first fin and a second gate on the second fin. 
 
     
     
       2. The method of  claim 1 , wherein the first doped oxide layer comprises boron. 
     
     
       3. The method of  claim 1 , wherein the first fin forms a portion of an NFET. 
     
     
       4. The method of  claim 1 , wherein the second doped oxide layer comprises phosphorus. 
     
     
       5. The method of  claim 1 , wherein the second doped oxide layer comprises arsenic. 
     
     
       6. The method of  claim 1 , wherein the oxide deposited between the first fin and the second fin is an undoped oxide. 
     
     
       7. The method of  claim 1 , wherein the first fin and the second fin each further comprise a hard mask cap and sidewall spacers. 
     
     
       8. The method of  claim 7 , wherein the first doped oxide spacer is arranged beneath the sidewall spacers of the first fin, and the second doped oxide spacer is arranged beneath the sidewall spacers of the second fin. 
     
     
       9. A method of making a semiconductor device, the method comprising:
 forming a first fin of a first transistor in a substrate; 
 forming a second fin of a second transistor in the substrate; 
 disposing a first doped oxide layer comprising a p-type dopant onto the first fin and the second fin; 
 disposing a mask over the first fin and removing the first doped oxide layer from the second fin; 
 removing the mask and disposing a second doped oxide layer onto the first doped oxide layer over the first fin and directly onto the second fin, the second doped oxide layer comprising an n-type dopant; 
 etching to recess the first doped oxide layer and the second doped oxide layer, leaving a layer of the first doped oxide layer on the first fin as a first doped oxide spacer and a layer of the second doped oxide layer on the second fin as a second doped oxide spacer; 
 annealing, after etching to recess, by a thermal process and under conditions sufficient to drive in the first dopant into a portion of the first fin and the second dopant into a portion of the second fin, and to drive the first dopant into the substrate beneath the first fin and the second dopant into the substrate beneath the second fin; 
 removing the first doped oxide spacer from the first fin and the second doped oxide spacer from the second fin; 
 depositing an oxide between the first fin and the second fin; and 
 forming a first gate on the first fin and a second gate on the second fin. 
 
     
     
       10. The method of  claim 9 , wherein the first doped oxide layer comprises boron. 
     
     
       11. The method of  claim 9 , wherein the first fin forms a portion of an NFET. 
     
     
       12. The method of  claim 9 , wherein the second doped oxide layer comprises phosphorus. 
     
     
       13. The method of  claim 9 , wherein the second doped oxide layer comprises arsenic. 
     
     
       14. The method of  claim 9 , wherein the oxide deposited between the first fin and the second fin is an undoped oxide. 
     
     
       15. The method of  claim 9 , wherein the first fin and the second fin each further comprise a hard mask cap and sidewall spacers. 
     
     
       16. The method of  claim 15 , wherein the first doped oxide spacer is arranged beneath the sidewall spacers of the first fin, and the second doped oxide spacer is arranged beneath the sidewall spacers of the second fin.