Receiver for receiving differential signal, IC including receiver, and display device

Abstract

The transmission delay time of a receiver for receiving a differential signal is reduced. A first amplifier circuit is provided in an input stage of the receiver, and a second amplifier circuit is provided in an output stage of the receiver. The first amplifier circuit is a differential input, differential output amplifier circuit. The second amplifier circuit is a differential input, single-ended output amplifier circuit. A first power supply voltage and a second power supply voltage are input as a high-level power supply voltage and a low-level power supply voltage to the first amplifier circuit and the second amplifier circuit, respectively. The withstand voltage of transistors of a differential pair of the first amplifier circuit is higher than the withstand voltage of another transistor included in the first amplifier circuit and a transistor included in the second amplifier circuit.

The invention claimed is: 
     
       1. A receiver configured to receive a first differential signal and output a first single-ended signal, the receiver comprising:
 a first input terminal; 
 a second input terminal; 
 a first output terminal; 
 a first amplifier circuit; and 
 a second amplifier circuit, 
 wherein the first input terminal and the second input terminal are input terminals for the first differential signal, 
 wherein the first output terminal is an output terminal for the first single-ended signal, 
 wherein the first amplifier circuit is a differential input, differential output amplifier circuit, 
 wherein the second amplifier circuit is a differential input, single-ended output amplifier circuit, 
 wherein one of two input terminals of the first amplifier circuit is electrically connected to the first input terminal, and the other thereof is electrically connected to the second input terminal, 
 wherein one of two output terminals of the first amplifier circuit is electrically connected to one of two input terminals of the second amplifier circuit, and the other thereof is electrically connected to the other input terminal of the second amplifier circuit, 
 wherein an output terminal of the second amplifier circuit is electrically connected to the first output terminal, 
 wherein a differential pair of the first amplifier circuit comprises a first transistor and a second transistor, 
 wherein a differential pair of the second amplifier circuit comprises a third transistor and a fourth transistor, and 
 wherein a withstand voltage of the first transistor and the second transistor is higher than a withstand voltage of the third transistor and the fourth transistor. 
 
     
     
       2. The receiver according to  claim 1 ,
 wherein the first transistor and the second transistor are n-channel transistors, and 
 wherein the third transistor and the fourth transistor are p-channel transistors. 
 
     
     
       3. The receiver according to  claim 1 ,
 wherein a first power supply voltage is the same as a high-level power supply voltage for a circuit to which the first single-ended signal is input, and 
 wherein a second power supply voltage is the same as a low-level power supply voltage for the circuit. 
 
     
     
       4. The receiver according to  claim 1 ,
 wherein the first amplifier circuit comprises a fifth transistor and a sixth transistor, 
 wherein the second amplifier circuit comprises a seventh transistor and an eighth transistor, 
 wherein the fifth transistor is configured to generate a first bias current to be supplied to the differential pair of the first amplifier circuit, 
 wherein the sixth transistor is configured to turn off the fifth transistor, 
 wherein the seventh transistor is configured to generate a second bias current to be supplied to the differential pair of the second amplifier circuit, and 
 wherein the eighth transistor is configured to turn off the seventh transistor. 
 
     
     
       5. The receiver according to  claim 4 ,
 wherein the first output terminal is electrically connected to a pull-up circuit, and 
 wherein the pull-up circuit is active when the fifth transistor and the seventh transistor are off. 
 
     
     
       6. The receiver according to  claim 4 ,
 wherein the first output terminal is electrically connected to a pull-down circuit, and 
 wherein the pull-down circuit is active when the fifth transistor and the seventh transistor are off. 
 
     
     
       7. The receiver according to  claim 4 ,
 wherein the first output terminal is electrically connected to a latch circuit, and 
 wherein the latch circuit is active when the fifth transistor and the seventh transistor are off. 
 
     
     
       8. The receiver according to  claim 1 , wherein the first amplifier circuit is a folded cascode operational amplifier. 
     
     
       9. The receiver according to  claim 1 , wherein the second amplifier circuit is a buffer operational amplifier. 
     
     
       10. A display device comprising:
 a pixel array; 
 a gate driver circuit; and 
 a driver IC comprising an interface circuit configured to receive an image signal, 
 wherein the interface circuit comprises the receiver according  claim 1 , and 
 wherein the gate driver circuit and the driver IC are electrically connected to the pixel array. 
 
     
     
       11. A receiver configured to receive a first differential signal and output a first single-ended signal, the receiver comprising:
 a first input terminal; 
 a second input terminal; 
 a first output terminal; 
 a first amplifier circuit; and 
 a second amplifier circuit, 
 wherein the first input terminal and the second input terminal are input terminals for the first differential signal, 
 wherein the first output terminal is an output terminal for the first single-ended signal, 
 wherein the first amplifier circuit is a differential input, differential output amplifier circuit, 
 wherein the second amplifier circuit is a differential input, single-ended output amplifier circuit, 
 wherein one of two input terminals of the first amplifier circuit is electrically connected to the first input terminal, and the other thereof is electrically connected to the second input terminal, 
 wherein one of two output terminals of the first amplifier circuit is electrically connected to one of two input terminals of the second amplifier circuit, and the other thereof is electrically connected to the other input terminal of the second amplifier circuit, 
 wherein an output terminal of the second amplifier circuit is electrically connected to the first output terminal, 
 wherein a differential pair of the first amplifier circuit comprises a first transistor and a second transistor, 
 wherein a differential pair of the second amplifier circuit comprises a third transistor and a fourth transistor, and 
 wherein a gate insulating layer of each of the first transistor and the second transistor is thicker than a gate insulating layer of each of the third transistor and the fourth transistor. 
 
     
     
       12. The receiver according to  claim 11 ,
 wherein the first transistor and the second transistor are n-channel transistors, and 
 wherein the third transistor and the fourth transistor are p-channel transistors. 
 
     
     
       13. The receiver according to  claim 11 ,
 wherein a first power supply voltage is the same as a high-level power supply voltage for a circuit to which the first single-ended signal is input, and 
 wherein a second power supply voltage is the same as a low-level power supply voltage for the circuit. 
 
     
     
       14. The receiver according to  claim 11 ,
 wherein the first amplifier circuit comprises a fifth transistor and a sixth transistor, 
 wherein the second amplifier circuit comprises a seventh transistor and an eighth transistor, 
 wherein the fifth transistor is configured to generate a first bias current to be supplied to the differential pair of the first amplifier circuit, 
 wherein the sixth transistor is configured to turn off the fifth transistor, 
 wherein the seventh transistor is configured to generate a second bias current to be supplied to the differential pair of the second amplifier circuit, and 
 wherein the eighth transistor is configured to turn off the seventh transistor. 
 
     
     
       15. The receiver according to  claim 14 ,
 wherein the first output terminal is electrically connected to a pull-up circuit, and 
 wherein the pull-up circuit is active when the fifth transistor and the seventh transistor are off. 
 
     
     
       16. The receiver according to  claim 14 ,
 wherein the first output terminal is electrically connected to a pull-down circuit, and 
 wherein the pull-down circuit is active when the fifth transistor and the seventh transistor are off. 
 
     
     
       17. The receiver according to  claim 14 ,
 wherein the first output terminal is electrically connected to a latch circuit, and 
 wherein the latch circuit is active when the fifth transistor and the seventh transistor are off. 
 
     
     
       18. The receiver according to  claim 11 , wherein the first amplifier circuit is a folded cascode operational amplifier. 
     
     
       19. The receiver according to  claim 11 , wherein the second amplifier circuit is a buffer operational amplifier. 
     
     
       20. A display device comprising:
 a pixel array; 
 a gate driver circuit; and 
 a driver IC comprising an interface circuit configured to receive an image signal, 
 wherein the interface circuit comprises the receiver according  claim 11 , and 
 wherein the gate driver circuit and the driver IC are electrically connected to the pixel array.