Reproducible stochastic rounding for out of order processors

Abstract

A method for generating a random number for use in a stochastic rounding operation is provided. The method includes executing an instruction that causes at least two operands to produce an intermediate result and incrementing a state of a random number generator. The method d further includes causing the random number generator to generate a random number in accordance with the state and producing a final result by utilizing the random number to determine a rounding of the intermediate result.

What is claimed is: 
     
       1. A computer-implemented method for managing hardware mechanisms to create cross platform reproducible results that can be utilized in hardware testing, code validation, computational biochemistry, and cognitive computing, the managing hardware mechanisms comprising generating a random number for use in a stochastic rounding operation executed by a processor coupled to a memory, comprising:
 setting a state of a random number generator to a known correct initial value upon initializing an instruction, the known correct initial value comprising an instruction address contained in the processor that is not alterable by a virtual address translation; 
 multiplying at least two operands to produce an intermediate result, the random number generator incrementing the state in correspondence with the intermediate result and on each branch taken, the random number generator setting the state to a prior state in the case of a branch wrongly taken; 
 causing the random number generator to generate the random number in accordance with the state; and 
 producing a final result by utilizing the random number to determine a rounding of the intermediate result. 
 
     
     
       2. The computer-implemented method of  claim 1 , wherein the state of the random number generator is loaded to a predefined state. 
     
     
       3. The computer-implemented method of  claim 1 , wherein the random number preserves a full probability distribution of the rounding of the intermediate result. 
     
     
       4. The computer-implemented method of  claim 1 , wherein the final result comprises a same number of bits as one of the at least two operands. 
     
     
       5. The computer-implemented method of  claim 1 , wherein the instruction causes multiple sets of the at least two operands to be multiplied to generate a plurality of intermediate results. 
     
     
       6. The computer-implemented method of  claim 1 , wherein the random number is one of a plurality of random numbers, wherein the intermediate result is one of a plurality of intermediate results, wherein each of the plurality of random numbers corresponds to one of a plurality of intermediate results based on the correspondence between each incremented state of the random number generator and the plurality of intermediate results. 
     
     
       7. The computer-implemented method of  claim 1 , wherein a least significant bit of the final result is rounded up or down based on the random number. 
     
     
       8. A computer program product, the computer program product comprising a computer readable storage medium having program instructions for managing hardware mechanisms to create cross platform reproducible results that can be utilized in hardware testing, code validation, computational biochemistry, and cognitive computing embodied therewith, the managing hardware mechanisms comprising generating a random number for use in a stochastic rounding operation executed, the program instructions executable by a processor to cause the processor to perform:
 setting a state of a random number generator to a known correct initial value upon initializing an instruction, the known correct initial value comprising an instruction address contained in the processor that is not alterable by a virtual address translation; 
 multiplying at least two operands to produce an intermediate result, the random number generator incrementing the state in correspondence with the intermediate result and on each branch taken, the random number generator setting the state to a prior state in the case of a branch wrongly taken; 
 causing the random number generator to generate the random number in accordance with the state; and 
 producing a final result by utilizing the random number to determine a rounding of the intermediate result. 
 
     
     
       9. The computer program product of  claim 8 , wherein the state of the random number generator is loaded to a predefined state. 
     
     
       10. The computer program product of  claim 8 , wherein the random number preserves a full probability distribution of the rounding of the intermediate result. 
     
     
       11. The computer program product of  claim 8 , wherein the final result comprises a same number of bits as one of the at least two operands. 
     
     
       12. The computer program product of  claim 8 , wherein the instruction causes multiple sets of the at least two operands to be multiplied to generate a plurality of intermediate results. 
     
     
       13. The computer program product of  claim 8 , wherein the random number is one of a plurality of random numbers, wherein the intermediate result is one of a plurality of intermediate results, wherein each of the plurality of random numbers corresponds to one of a plurality of intermediate results based on the correspondence between each incremented state of the random number generator and the plurality of intermediate results. 
     
     
       14. The computer program product of  claim 8 , wherein a least significant bit of the final result is rounded up or down based on the random number. 
     
     
       15. A system comprising a processor and a memory storing program instructions for managing hardware mechanisms to create cross platform reproducible results that can be utilized in hardware testing, code validation, computational biochemistry, and cognitive computing thereon, the managing hardware mechanisms comprising generating a random number for use in a stochastic rounding operation executed, the program instructions executable by a processor to cause the system to perform:
 setting a state of a random number generator to a known correct initial value upon initializing an instruction, the known correct initial value comprising an instruction address contained in the processor that is not alterable by a virtual address translation; 
 multiplying at least two operands to produce an intermediate result, the random number generator incrementing the state in correspondence with the intermediate result and on each branch taken, the random number generator setting the state to a prior state in the case of a branch wrongly taken; 
 causing the random number generator to generate the random number in accordance with the state; and 
 producing a final result by utilizing the random number to determine a rounding of the intermediate result. 
 
     
     
       16. The system of  claim 15 , wherein the state of the random number generator is loaded to a predefined state. 
     
     
       17. The system of  claim 15 , wherein the random number preserves a full probability distribution of the rounding of the intermediate result. 
     
     
       18. The system of  claim 15 , wherein the final result comprises a same number of bits as one of the at least two operands. 
     
     
       19. The system of  claim 15 , wherein the instruction causes multiple sets of the at least two operands to be multiplied to generate a plurality of intermediate results. 
     
     
       20. The system of  claim 15 , wherein the random number is one of a plurality of random numbers, wherein the intermediate result is one of a plurality of intermediate results, wherein each of the plurality of random numbers corresponds to one of a plurality of intermediate results based on the correspondence between each incremented state of the random number generator and the plurality of intermediate results.