Multiprocessor system

Abstract

The present invention realizes a functional safety of a multiprocessor system without tightly coupling processor elements. When causing a plurality of processor elements to execute the same data processing and realizing a functional safety of the processor element, there is adopted a bus interface unit that performs control of performing safety measure processing when the non-coincidence of access requests issued from the processor elements has been fixed, and of starting access processing responding the access request when these access requests coincide with one another.

What is claimed is: 
     
       1. A multiprocessor system comprising:
 a plurality of processors; 
 a bus slave circuit accessible by the plurality of processors; 
 a bus disposed between the plurality of processors and the bus slave circuit; and 
 a fail-safe circuit configured to perform a fail-safe process to maintain functional safety on the multiprocessor system, 
 wherein the plurality of processors includes first, second and third processors which perform a process in lock-step, and 
 wherein the fail-safe circuit configured to:
 when a first bus access request issued by the first processor is consistent with a second bus access request issued by the second processor and a third bus access request issued by the third processor within a predetermined period after the first bus access request is issued, execute a bus access request based on the first, second and third bus access requests, 
 when the first bus access request issued by the first processor is consistent with the second bus access request issued by the second processor and is not consistent with the third bus access request issued by the third processor within the predetermined period after the first bus access request is issued, execute a bus access request based on the first and second bus access requests and execute the fail-safe process for the third bus access request, and 
 when the first bus access request issued by the first processor is not consistent with the second bus access request issued by the second processor and the third bus access request issued by the third processor within the predetermined period after the first bus access request is issued, execute the fail-safe process for the first, second and third bus access requests. 
 
 
     
     
       2. The multiprocessor system according to  claim 1 , wherein the fail-safe process is a cancel of the inconsistent bus access request. 
     
     
       3. The multiprocessor system according to  claim 1 , wherein the fail-safe process is a stop instruction to a processor which issues the inconsistent bus access request. 
     
     
       4. The multiprocessor system according to  claim 1 , wherein the fails-safe process is a reset instruction to a processor which issues the inconsistent bus access request. 
     
     
       5. The multiprocessor system according to  claim 2 , wherein the fail-safe process further includes an error notification to an outside of the multiprocessor system. 
     
     
       6. The multiprocessor system according to  claim 1 , wherein the bus includes the fail-safe circuit. 
     
     
       7. The multiprocessor system according to  claim 1 , wherein the multiprocessor system comprises a single-chip.