Magnetoelectric memory cells with domain-wall-mediated switching

Abstract

A magnetoelectric memory cell with domain-wall-mediated switching is implemented using a split gate architecture. The split gate architecture allows a domain wall to be trapped within a magnetoelectric antiferromagnetic (MEAF) active layer. An extension of this architecture applies to multiple-gate linear arrays that can offer advantages in memory density, programmability, and logic functionality. Applying a small anisotropic in-plane shear strain to the MEAF can block domain wall precession to improve reliability and speed of switching.

We claim: 
     
       1. A magnetoelectric memory device comprising:
 an electrode; 
 a magnetoelectric layer coupled to the top of the electrode; 
 a first set gate on a top of the magnetoelectric layer towards one end of the magnetoelectric layer; 
 a second set gate on the top of the magnetoelectric layer towards an opposite end of the magnetoelectric layer from the first set gate; 
 a control gate on the top of the magnetoelectric layer and positioned between the first set gate and the second set gate. 
 
     
     
       2. The device of  claim 1 , wherein the magnetoelectric layer is a magnetoelectric antiferromagnetic layer. 
     
     
       3. The device of  claim 1 , wherein the magnetoelectric layer comprises chromia, boron doped chromia, chromia alloy, or boron doped chromia alloy. 
     
     
       4. The device of  claim 1 , further comprising a means for applying an anisotropic in-plane shear strain to the device. 
     
     
       5. The device of  claim 1 , further comprising a piezoelectric element below the electrode, a first contact pad on top of the piezoelectric element, and a second contact pad on top of the piezoelectric element. 
     
     
       6. The device of  claim 1 , further comprising an anisotropic substrate below the electrode. 
     
     
       7. The device of  claim 1 , further comprising a patterned structure for anisotropic thermal expansion, the patterned structure adjacent to the magnetoelectric layer such that the magnetoelectric layer, the first set gate, the second set gate, and the control gate are within the patterned structure. 
     
     
       8. The device of  claim 1 , further comprising:
 a transistor, wherein the drain of the transistor is electrically connected to the electrode, the source of the transistor is electrically connected to a ground line, and the gate of the transistor is electrically connected to a word line; 
 a magnetic tunnel junction on top of the magnetoelectric layer; and 
 a bit line electrically connected to a ferromagnetic layer of the magnetic tunnel junction. 
 
     
     
       9. A method of operating the device of  claim 1 , comprising:
 initializing the device to enforce a domain wall in the magnetoelectric layer; 
 writing a logical ONE or a logical ZERO to the device, wherein writing to the device comprises applying a positive voltage to the first set gate, applying a negative voltage to the second set gate, and applying a positive or negative voltage to the control gate; and thereby storing a logical ONE or logical ZERO into the memory device according to the polarity of the voltage applied to the control gate. 
 
     
     
       10. The method of  claim 9 , wherein the device further comprises: a transistor, wherein the drain of the transistor is electrically connected to the electrode, the source of the transistor is electrically connected to a ground line, and the gate of the transistor is electrically connected to a word line; a magnetic tunnel junction on top of the magnetoelectric layer; and a bit line electrically connected to a ferromagnetic layer on the magnetic tunnel junction; the method further comprising:
 reading a logical ONE or a logical ZERO from the device, wherein reading from the device comprises applying a logical ONE to the word line and comparing the resistance between the bit line and the ground line. 
 
     
     
       11. The method of  claim 9 , wherein writing a logical ONE in the memory device comprises applying a positive polarity to the control gate. 
     
     
       12. The method of  claim 9 , wherein writing a logical ZERO in the memory device comprises applying a negative polarity to the control gate. 
     
     
       13. The method of  claim 9 , wherein initializing the device comprises applying a first voltage to the first set gate, applying a second voltage to the second set gate, and applying a third voltage to the control gate until a domain wall is enforced. 
     
     
       14. A linear magnetoelectric memory device array comprising:
 an electrode; 
 a magnetoelectric layer coupled to the top of the electrode; 
 a plurality of shared set gates in an alternating pattern of positive polarity and negative polarity on the magnetoelectric layer; 
 a plurality of control gates interspersed between the plurality of shared set gates on the magnetoelectric layer. 
 
     
     
       15. The device array of  claim 14 , wherein the magnetoelectric layer is a magnetoelectric antiferromagnetic layer. 
     
     
       16. The device array of  claim 14 , wherein the magnetoelectric layer comprises chromia, boron doped chromia, chromia alloy, or boron doped chromia alloy. 
     
     
       17. The device array of  claim 14 , further comprising a means for applying an anisotropic in-plane shear strain to the device. 
     
     
       18. The device array of  claim 17 , wherein the means for applying the anisotropic in-plane shear strain comprises a piezoelectric element, a first contact pad on top of the piezoelectric element below the electrode, and a second contact pad on top of the piezoelectric element. 
     
     
       19. The device of  claim 17 , wherein the means for applying the anisotropic in-plane shear strain comprises an anisotropic substrate below the electrode. 
     
     
       20. The device of  claim 17 , wherein the means for applying the anisotropic in-plane shear strain comprises a patterned structure around the device array for anisotropic thermal expansion.