Punch through stopper in bulk finFET device

Abstract

A method of forming a semiconductor device that includes forming a fin structure from a bulk semiconductor substrate and forming an isolation region contacting a lower portion of a sidewall of the fin structure, wherein an upper portion of the sidewall of the fin structure is exposed. A sacrificial spacer is formed on the upper portion of the sidewall of the fin structure. The isolation regions are recessed to provide an exposed section of the sidewall of the fin structure. A doped semiconductor material is formed on the exposed section of the lower portion of the sidewall of the fin structure. Dopant is diffused from the doped semiconductor material to a base portion of the fin structure.

What is claimed is: 
     
       1. A method for forming a semiconductor device comprising:
 forming a fin structure from a bulk semiconductor substrate; 
 forming an isolation region contacting a lower portion of a sidewall of the fin structure, wherein an upper portion of the sidewall of the fin structure is exposed; 
 forming a gate structure on a channel region portion of the fin structure after said forming the isolation region; 
 forming a sacrificial spacer on the gate structure before recessing the isolation region; 
 recessing the isolation region to provide an exposed section of the lower portion of the sidewall of the fin structure; 
 forming a doped semiconductor material on the exposed section of the fin structure; 
 diffusing dopant from the doped semiconductor material to a base portion of the fin structure; and 
 removing the sacrificial spacer in its entirety. 
 
     
     
       2. The method of  claim 1 , wherein the dopant that is diffused from the doped semiconductor material to the base portion of the fin structure has an opposite conductivity as a source region dopant and a drain region dopant. 
     
     
       3. The method of  claim 1 , wherein the gate structure is a replacement gate structure comprised of a sacrificial material, wherein the replacement gate structure is removed after said diffusing the dopant from the doped semiconductor material to the base portion of the fin structure and a functional gate is formed in the place of the replacement gate structure. 
     
     
       4. The method of  claim 3 , wherein the forming of the replacement gate on the fin structure comprises:
 depositing at least one sacrificial material layer on the fin structure; and 
 patterning the at least one sacrificial material layer to remove the sacrificial material from a source region portion and a drain region portion of the fin structure so that a remaining portion of the at least one sacrificial material layer is present on the channel region portion of the fin structure. 
 
     
     
       5. The method of  claim 1 , wherein forming the isolation region comprises:
 depositing a dielectric material in contact with an entire sidewall of the fin structure; and 
 recessing the dielectric material to expose the upper portion of the sidewall. 
 
     
     
       6. The method of  claim 1 , wherein the forming of the sacrificial spacer comprises:
 conformally depositing a blanket layer of a dielectric material; and 
 anisotropically etching the blanket layer of the dielectric material to remove horizontally orientated portions of the blanket layer of the dielectric material, wherein vertically orientated portions of the blanket layer of the dielectric material remain on the upper portion of the fin structure. 
 
     
     
       7. The method of  claim 1 , wherein said forming the doped semiconductor material on the exposed section of the sidewall of the fin structure comprises epitaxial deposition of a silicon including material that is in situ doped with an n-type or p-type dopant. 
     
     
       8. The method of  claim 1 , wherein said diffusing dopant from the doped semiconductor material to a base portion of the fin structure comprises thermal annealing selected from the group consisting of rapid thermal anneal, laser annealing and combinations thereof. 
     
     
       9. The method of  claim 1  further comprising forming source and drain regions in contact with the upper portion of the sidewall of the fin structure. 
     
     
       10. A method for forming a semiconductor device comprising:
 forming a fin structure from a bulk semiconductor substrate; 
 forming an isolation region contacting a lower portion of a sidewall of the fin structure, wherein an upper portion of the sidewall of the fin structure is exposed; 
 forming a gate structure on a channel region portion of the fin structure; 
 forming a sacrificial spacer on the upper portion of the sidewall of the fin structure; 
 recessing the isolation region to provide an exposed section of the lower portion of the sidewall of the fin structure; 
 forming a doped semiconductor material on the exposed section of the fin structure; 
 diffusing dopant from the doped semiconductor material to a base portion of the fin structure, wherein the dopant that is diffused from the doped semiconductor material to the base portion of the fin structure has an opposite conductivity as a source region dopant and a drain region dopant; and 
 removing the sacrificial spacer in its entirety. 
 
     
     
       11. The method of  claim 10 , wherein the gate structure is a replacement gate structure comprised of a sacrificial material, wherein the replacement gate structure is removed after said diffusing the dopant from the doped semiconductor material to the base portion of the fin structure and a functional gate is formed in the place of the replacement gate structure. 
     
     
       12. The method of  claim 11 , wherein the forming of the replacement gate on the fin structure comprises:
 depositing at least one sacrificial material layer on the fin structure; and 
 patterning the at least one sacrificial material layer to remove the sacrificial material from a source region portion and a drain region portion of the fin structure so that a remaining portion of the at least one sacrificial material layer is present on the channel region portion of the fin structure. 
 
     
     
       13. The method of  claim 10 , wherein forming the isolation region comprises:
 depositing a dielectric material in contact with an entire sidewall of the fin structure; and 
 recessing the dielectric material to expose the upper portion of the sidewall. 
 
     
     
       14. The method of  claim 10 , wherein the forming of the sacrificial spacer comprises:
 conformally depositing a blanket layer of a dielectric material; and 
 anisotropically etching the blanket layer of the dielectric material to remove horizontally orientated portions of the blanket layer of the dielectric material, wherein vertically orientated portions of the blanket layer of the dielectric material remain on the upper portion of the fin structure. 
 
     
     
       15. The method of  claim 10 , wherein said forming the doped semiconductor material on the exposed section of the sidewall of the fin structure comprises epitaxial deposition of a silicon including material that is in situ doped with an n-type or p-type dopant. 
     
     
       16. The method of  claim 10 , wherein said diffusing dopant from the doped semiconductor material to a base portion of the fin structure comprises thermal annealing selected from the group consisting of rapid thermal anneal, laser annealing and combinations thereof. 
     
     
       17. The method of  claim 10  further comprising forming source and drain regions in contact with the upper portion of the sidewall of the fin structure.