CMOS with middle of line processing of III-V material on mandrel

Abstract

A method includes forming first structures on a first portion of a silicon substrate and second structures on a second portion of the substrate; forming spacers on the first structures; forming dummy gates on the first and second structures; depositing a first interlayer dielectric on the dummy gates; removing the dummy gates from the second structures; forming metal gates on the second structures; performing an anneal; forming recess areas in the first interlayer dielectric; removing the spacers from the first structures; epitaxially growing sidewalls on the first structures; removing portions of the first structures outside the dummy gates from the first portion; depositing a second interlayer dielectric on the first portion; removing the dummy gates from the first portion; removing portions of the first structures previously under the dummy gates from the first portion; and forming metal gates on the first structures.

What is claimed is: 
     
       1. A structure, comprising:
 a substrate having a handle layer of silicon, a buried oxide layer on the handle layer, an NFET layer of silicon-on-insulator on an NFET portion of the buried oxide layer, and a PFET layer of silicon-on-insulator or SiGe on a PFET portion of the buried oxide layer; 
 fins in the silicon-on-insulator or SiGe of the PFET layer; 
 source/drains in the PFET layer; 
 one or more first metal gates on the fins, wherein the fins, the source/drains in the PFET layer, and the one or more first metal gates on the fins are annealed; 
 channel structures of III-V material in the silicon-on-insulator in the NFET portion, wherein the channel structures are not annealed; 
 source/drains in the NFET portion; and 
 one or more second metal gates on the channel structures in the NFET layer. 
 
     
     
       2. The structure of  claim 1 , further comprising a high-k dielectric layer on the channel structures in the NFET layer. 
     
     
       3. The structure of  claim 1 , wherein the one or more second metal gates are capped. 
     
     
       4. The structure of  claim 3 , wherein the one or more second metal gates are capped with a nitride. 
     
     
       5. The structure of  claim 1 , wherein the channel structures of III-V material are formed from a first III-V material and wherein the source/drains in the NFET portion include a second III-V material that is different from the first III-V material. 
     
     
       6. The structure of  claim 5 , wherein the first III-V material and the second III-V material are each selected from the group consisting of gallium arsenide (GaAs), aluminum arsenide (AlAs), gallium phosphide (GaP), gallium nitride (GaN), gallium arsenide phosphide (GaAsP), gallium indium arsenide antimony phosphide (GaInAsSbP), aluminum gallium arsenide (AlGaAs), aluminum gallium indium arsenide (AlGaInAs), indium arsenide (InAs), indium gallium phosphide (InGaP), indium gallium arsenide (InGaAs), indium arsenide antimony phosphide (InAsSbP), indium gallium aluminum phosphide (InGaAlP), and combinations of the foregoing. 
     
     
       7. A structure, comprising:
 a substrate having a handle layer of silicon, a buried oxide layer on the handle layer, an NFET layer of silicon-on-insulator on an NFET portion of the buried oxide layer, and a PFET layer of silicon-on-insulator or SiGe on a PFET portion of the buried oxide layer; 
 fins in the silicon-on-insulator or SiGe of the PFET layer; 
 source/drains in the PFET layer; 
 one or more first metal gates on the fins; 
 channel structures formed in the silicon-on-insulator in the NFET portion; 
 source/drains in the NFET portion; and 
 one or more second metal gates on the channel structures in the NFET layer; 
 wherein the channel structures formed in the silicon-on-insulator in the NFET portion are formed from a first III-V material and wherein the source/drains in the NFET portion include a second III-V material that is different from the first III-V material. 
 
     
     
       8. The structure of  claim 7 , wherein the first III-V material and the second III-V material are selected from the group consisting of gallium arsenide (GaAs), aluminum arsenide (AlAs), gallium phosphide (Gap), gallium nitride (GaN), gallium arsenide phosphide (GaAsP), gallium indium arsenide antimony phosphide (GaInAsSbP), aluminum gallium arsenide (AlGaAs), aluminum gallium indium arsenide (AlGaInAs), indium arsenide (InAs), indium gallium phosphide (InGaP), indium gallium arsenide (InGaAs), indium arsenide antimony phosphide (InAsSbP), indium gallium aluminum phosphide (InGaAlP), and combinations of the foregoing. 
     
     
       9. The structure of  claim 7 , wherein the first III-V material is selected from the group consisting of InGaAs and GaAs, and wherein the second III-V material is selected from the group consisting of InGaAs and InAs.