Grated MIM capacitor to improve capacitance

Abstract

An on-chip metal-insulator-metal (MIM) capacitor with enhanced capacitance is provided by forming the MIM capacitor along sidewall surfaces and a bottom surface of each trench of a plurality of trenches formed in a back-end-of-the-line (BEOL) metallization stack to increase a surface area of the MIM capacitor.

What is claimed is: 
     
       1. A semiconductor structure comprising:
 a first lower interconnect structure embedded in a portion of a first dielectric material layer and a second lower interconnect structure embedded in another portion of the first dielectric material layer; 
 a second dielectric material layer located over the first dielectric material layer; 
 a metal-insulator-metal (MIM) capacitor located along sidewall surfaces and a bottom surface of each trench of a plurality of trenches present in an upper portion of the second dielectric material layer and on a topmost surface of the second dielectric material layer; 
 a third dielectric material layer located over the MIM capacitor and the second dielectric material layer; 
 a first upper interconnect structure extending through the third dielectric material layer and the second dielectric material layer to vertically contact the first lower interconnect structure, wherein the first upper interconnect structure laterally contacts a first end of the MIM capacitor; and 
 a second upper interconnect structure extending through the third dielectric material layer and the second dielectric material layer to vertically contact the second lower interconnect structure, wherein the second upper interconnect structure laterally contacts a second end of the MIM capacitor opposite the first end. 
 
     
     
       2. The semiconductor structure of  claim 1 , wherein the MIM capacitor comprises a bottom electrode located along the sidewall surfaces and the bottom surface of each trench of the plurality of trenches and on the topmost surfaces of the portions of the second dielectric material layer defining the plurality of trenches, a first capacitor electric located on the bottom electrode, a middle electrode located on the first capacitor electric, a second capacitor electric located on the middle electrode and a top electrode located on the second capacitor electrode. 
     
     
       3. The semiconductor structure of  claim 2 , wherein the first upper interconnect structure laterally contacts an end wall of the bottom electrode and an end wall of the top electrode, and the second upper interconnect structure laterally contacts an end wall of the middle electrode. 
     
     
       4. The semiconductor structure of  claim 2 , wherein a portion of the middle electrode overlaps a portion of the bottom electrode and a portion of the top electrode. 
     
     
       5. The semiconductor structure of  claim 2 , wherein the first upper interconnect structure laterally contacts an end wall of the first capacitor dielectric and an end wall the second upper capacitor dielectric, and the second interconnect structure laterally contacts another end wall of the first capacitor dielectric and another end wall of the second capacitor dielectric. 
     
     
       6. The semiconductor structure of  claim 2 , wherein each of the bottom electrode, the middle electrode and the top electrode comprises Ti, TiN, Ta, TaN, or Cu. 
     
     
       7. The semiconductor structure of  claim 2 , wherein each of the first capacitor dielectric and the second capacitor dielectric comprises silicon dioxide, silicon nitride or a high-k dielectric material. 
     
     
       8. The semiconductor structure of  claim 1 , wherein each of the first upper interconnect structure and the second upper interconnect structure comprises a conductive via structure and a conductive line structure atop the conductive via structure, wherein the conductive via structure in the first upper interconnect structure laterally contacts the first end of the MIM capacitor, and the conductive via structure in the second upper interconnect structure laterally contacts the second end of the MIM capacitor. 
     
     
       9. The semiconductor structure of  claim 8 , wherein the conductive line structure in each of the first upper interconnect structure and the second upper interconnect structure has a topmost surface coplanar with a topmost surface of the third dielectric material layer. 
     
     
       10. The semiconductor structure of  claim 1 , wherein each of the first lower interconnect structure and the second lower interconnect structure has a topmost surface coplanar with a topmost surface of the first dielectric material layer.