Semiconductor arrangement with capacitor

Abstract

A semiconductor arrangement includes a logic region and a memory region. The memory region has an active region that includes a semiconductor device. The memory region also has a capacitor within one or more dielectric layers over the active region, where the capacitor is over the semiconductor device. The semiconductor arrangement also includes a protective ring within at least one of the logic region or the memory region and that separates the logic region from the memory region. The capacitor has a first electrode, a second electrode and an insulating layer between the first electrode and the second electrode, where the first electrode is substantially larger than other portions of the capacitor.

What is claimed is: 
     
       1. A method of forming a semiconductor arrangement, comprising:
 etching a first opening in a first dielectric layer to expose a metal contact in a second dielectric layer underlying the first dielectric layer, wherein the metal contact provides an electrical connection through the second dielectric layer to a semiconductor device; 
 etching a second opening in the first dielectric layer to expose a first portion of the second dielectric layer; 
 forming a first conductive layer in the first opening and the second opening, wherein a portion of the first conductive layer in the first opening defines a first electrode and a portion of the first conductive layer in the second opening defines a protective ring; 
 removing a portion of the first dielectric layer between the first electrode and the protective ring to expose a second portion of the second dielectric layer; and 
 forming an insulating layer over the first electrode, the second portion of the second dielectric layer, and the protective ring. 
 
     
     
       2. The method of  claim 1 , wherein the protective ring delineates between a memory region and a logic region of the semiconductor arrangement and the method comprises:
 forming a mask over the logic region prior to removing the portion of the first dielectric layer between the first electrode and the protective ring. 
 
     
     
       3. The method of  claim 2 , wherein the mask is formed over a portion of the first dielectric layer in the logic region to protect the portion of the first dielectric layer in the logic region from removal while removing the portion of the first dielectric layer between the first electrode and the protective ring. 
     
     
       4. The method of  claim 3 , comprising:
 removing the mask prior to forming the insulating layer, wherein forming the insulating layer comprises forming the insulating layer over the portion of the first dielectric layer in the logic region. 
 
     
     
       5. The method of  claim 4 , wherein the insulating layer contacts the second portion of the second dielectric layer and the portion of the first dielectric layer in the logic region. 
     
     
       6. The method of  claim 2 , comprising removing the mask prior to forming the insulating layer. 
     
     
       7. The method of  claim 1 , wherein the insulating layer contacts the first electrode, the second portion of the second dielectric layer, and the protective ring. 
     
     
       8. The method of  claim 1 , comprising:
 forming a second conductive layer over the insulating layer. 
 
     
     
       9. The method of  claim 8 , wherein the protective ring delineates between a memory region and a logic region of the semiconductor arrangement and the method comprises:
 forming a mask over the second conductive layer in the memory region; and 
 removing a portion of the second conductive layer and a portion of the insulating layer in the logic region. 
 
     
     
       10. The method of  claim 9 , wherein removing the portion of the second conductive layer and the portion of the insulating layer in the logic region exposes a logic contact in the first dielectric layer. 
     
     
       11. The method of  claim 10 , comprising:
 forming a second insulating layer over the second conductive layer and the logic contact; and 
 forming a via contact in the second insulating layer over the logic contact. 
 
     
     
       12. The method of  claim 1 , wherein etching the first opening and etching the second opening are performed concurrently. 
     
     
       13. A method of forming a semiconductor arrangement, comprising:
 forming a first conductive layer in a first opening defined in a first dielectric layer and a second opening defined in the first dielectric layer, wherein a portion of the first conductive layer in the first opening defines a first electrode and a portion of the first conductive layer in the second opening defines a protective ring; 
 removing a portion of the first dielectric layer between the first electrode and the protective ring to expose a second dielectric layer; and 
 forming an insulating layer in contact with a top surface of the first electrode, a top surface of the protective ring, and a top surface the second dielectric layer between the first electrode and the protective ring. 
 
     
     
       14. The method of  claim 13 , wherein the protective ring delineates between a memory region and a logic region of the semiconductor arrangement and the method comprises:
 forming a mask over the logic region prior to removing the portion of the first dielectric layer between the first electrode and the protective ring to protect a portion of the first dielectric layer in the logic region from removal while removing the portion of the first dielectric layer between the first electrode and the protective ring. 
 
     
     
       15. The method of  claim 14 , comprising:
 removing the mask prior to forming the insulating layer, wherein forming the insulating layer comprises forming the insulating layer over the portion of the first dielectric layer in the logic region. 
 
     
     
       16. The method of  claim 13 , comprising:
 forming a second conductive layer over the insulating layer, wherein the second conductive layer defines a second electrode. 
 
     
     
       17. The method of  claim 16 , wherein the protective ring delineates between a memory region and a logic region of the semiconductor arrangement and the method comprises:
 forming a mask over the second conductive layer in the memory region; and 
 removing a portion of the second conductive layer and a portion of the insulating layer in the logic region. 
 
     
     
       18. The method of  claim 17 , wherein removing the portion of the second conductive layer and the portion of the insulating layer in the logic region exposes a logic contact in the first dielectric layer. 
     
     
       19. The method of  claim 13 , wherein the first opening and the second opening are further defined in a third dielectric layer overlying the first dielectric layer. 
     
     
       20. A method of forming a semiconductor arrangement, comprising:
 etching a first opening in a first dielectric layer to expose a metal contact in a second dielectric layer underlying the first dielectric layer; 
 etching a second opening in the first dielectric layer to expose a first portion of the second dielectric layer; 
 forming a first conductive layer in the first opening and the second opening, wherein a portion of the first conductive layer in the first opening defines a first electrode and a portion of the first conductive layer in the second opening defines a protective ring; 
 removing a portion of the first dielectric layer between the first electrode and the protective ring to expose a second portion of the second dielectric layer; and 
 forming an insulating layer, wherein the insulating layer contacts a first sidewall of the protective ring and the first dielectric layer contacts a second sidewall of the protective ring.