Inventor · disambiguated record
Valeriu Beiu
Also filed as: BEIU VALERIU
7 granted patents·2 pending applications·48 citations·filing 1998–2002
83Inventor score
Top patents by PatentIndex Score
9 records- 0171US6259275B1Logic gate having reduced power dissipation and method of operation thereofRN2R L L C·Filed 2000·Granted Jul 10, 2001·17 cites·70 claims
- 0268US6580296B1Low power differential conductance-based logic gate and method of operation thereofRN2R L L C·Filed 2000·Granted Jun 17, 2003·16 cites·49 claims
- 0352US6502120B2Adder circuit employing logic gates having discrete weighted inputs and a method of operation therewithRN2R LLC·Filed 2001·Granted Dec 31, 2002·4 cites·24 claims
- 0451US6516331B2Microprocessor and a digital signal processor including adder and multiplier circuits employing logic gates having discrete and weighted inputsRN2R L L C·Filed 2001·Granted Feb 4, 2003·2 cites·20 claims
- 0542US2003009504A1Adder and multiplier circuits employing logic gates having discrete, weighted inputs and methods of performing combinatorial operations therewithRN2R L L C·Filed 2002·Application pending·0 cites
- 0642US2003028575A1A Microprocessor and a digital signal processor including adder and multiplier circuits employing logic gates having discrete and weighted inputsRN2R L L C·Filed 2002·Application pending·0 cites
- 0731US6430585B1Noise tolerant conductance-based logic gate and methods of operation and manufacturing thereofRN2R L L C·Filed 1999·Granted Aug 6, 2002·6 cites·80 claims
- 0829US6205458B1Adder and multiplier circuits employing logic gates having discrete, weighted inputs and methods of performing combinatorial operations therewithRN2R L L C·Filed 1998·Granted Mar 20, 2001·3 cites·8 claims
- 0926US6438572B1Adder having reduced number of internal layers and method of operation thereofRN2R L L C·Filed 1999·Granted Aug 20, 2002·0 cites·35 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →