Inventor · disambiguated record
Prathiba Kumar
Also filed as: KUMAR PRATHIBA
19 granted patents·1 pending application·80 citations·filing 2009–2016
93Inventor score
Top patents by PatentIndex Score
20 records- 0196US10528349B2Branch synthetic generation across multiple microarchitecture generationsIBM·Filed 2016·Granted Jan 7, 2020·16 cites·6 claims
- 0291US8838801B2Cloud optimization using workload analysisALAPATI SANGRAM·Filed 2012·Granted Sep 16, 2014·21 cites·14 claims
- 0389US8914515B2Cloud optimization using workload analysisALAPATI SANGRAM·Filed 2011·Granted Dec 16, 2014·15 cites·13 claims
- 0485US9921836B2Branch synthetic generation across multiple microarchitecture generationsIBM·Filed 2016·Granted Mar 20, 2018·3 cites·1 claims
- 0580US8607243B2Dynamic operating system optimization in parallel computingKUMAR PRATHIBA·Filed 2011·Granted Dec 10, 2013·6 cites·4 claims
- 0669US10353708B2Strided loading of non-sequential memory locations by skipping memory locations between consecutive loadsADVANCED MICRO DEVICES INC·Filed 2016·Granted Jul 16, 2019·2 cites·14 claims
- 0769US9519481B2Branch synthetic generation across multiple microarchitecture generationsIBM·Filed 2014·Granted Dec 13, 2016·1 cites·5 claims
- 0869US9032375B2Performance bottleneck identification toolKUMAR PRATHIBA·Filed 2011·Granted May 12, 2015·3 cites·15 claims
- 0969US8892949B2Effective validation of execution units within a processorIBM·Filed 2013·Granted Nov 18, 2014·2 cites·7 claims
- 1067US9129057B2Smart multiplexing of performance counters for performance measurementSADASIVAM SATISH K·Filed 2012·Granted Sep 8, 2015·3 cites·18 claims
- 1166US8930760B2Validating cache coherency protocol within a processorIBM·Filed 2012·Granted Jan 6, 2015·2 cites·20 claims
- 1265US8667255B2Measuring runtime coverage of architectural events of a microprocessorALAPATI SANGRAM·Filed 2010·Granted Mar 4, 2014·2 cites·20 claims
- 1362US8140901B2Validation of processors using a self-generating test case frameworkKUMAR PRATHIBA·Filed 2009·Granted Mar 20, 2012·3 cites·23 claims
- 1461US9021281B2Run-time task-level dynamic energy managementIBM·Filed 2013·Granted Apr 28, 2015·1 cites·6 claims
- 1559US9886274B2Branch synthetic generation across multiple microarchitecture generationsIBM·Filed 2016·Granted Feb 6, 2018·0 cites·1 claims
- 1658US9542183B2Branch synthetic generation across multiple microarchitecture generationsIBM·Filed 2016·Granted Jan 10, 2017·0 cites·1 claims
- 1750US9158640B2Tightly-coupled context-aware irritator thread creation for verification of microprocessorsIBM·Filed 2013·Granted Oct 13, 2015·0 cites·20 claims
- 1847US8904208B2Run-time task-level dynamic energy managementALAPATI SANGRAM·Filed 2011·Granted Dec 2, 2014·0 cites·12 claims
- 1947US8850266B2Effective validation of execution units within a processorALAPATI SANGRAM·Filed 2011·Granted Sep 30, 2014·0 cites·14 claims
- 2043US2012084028A1Framework and Methodology for a Real-Time Fine-Grained Power Profiling with Integrated ModelingKUMAR PRATHIBA·Filed 2010·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →