Inventor · disambiguated record
Keiichi Nishimuda
Also filed as: NISHIMUDA KEIICHI
3 granted patents·1 citations·filing 2008–2012
53Inventor score
Technology areasH10W
Top patents by PatentIndex Score
3 records- 0150US8418109B2Semiconductor integrated circuit with multi-cut via and automated layout method for the sameNISHIMUDA KEIICHI·Filed 2012·Granted Apr 9, 2013·1 cites·4 claims
- 0244US8020133B2Semiconductor integrated circuit with multi-cut via and automated layout method for the sameRENESAS ELECTRONICS CORP·Filed 2008·Granted Sep 13, 2011·0 cites·6 claims
- 0338US8271926B2Semiconductor integrated circuit with multi-cut via and automated layout method for the sameNISHIMUDA KEIICHI·Filed 2011·Granted Sep 18, 2012·0 cites·14 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →