Inventor · disambiguated record
Giovanna Dalla Libera
Also filed as: DALLA LIBERA GIOVANNA
18 granted patents·1 pending application·155 citations·filing 1997–2002
94Inventor score
Top patents by PatentIndex Score
19 records- 0175US6624015B2Method for manufacturing electronic devices having non-volatile memory cells and LV transistors with salicided junctionsST MICROELECTRONICS SRL·Filed 2001·Granted Sep 23, 2003·17 cites·12 claims
- 0271US6548857B2Low resistance contact structure for a select transistor of EEPROM memory cells in a NO-DPCC processST MICROELECTRONICS SRL·Filed 2002·Granted Apr 15, 2003·13 cites·17 claims
- 0370US6521957B2Method for forming a multilevel ROM memory in a dual gate CMOS process, and corresponding ROM memory cellST MICROELECTRONICS SRL·Filed 2000·Granted Feb 18, 2003·10 cites·7 claims
- 0466US6432762B1Memory cell for EEPROM devices, and corresponding fabricating processSGS THOMSON MICROELECTRONICS·Filed 2000·Granted Aug 13, 2002·9 cites·21 claims
- 0566US6268247B1Memory cell of the EEPROM type having its threshold set by implantation, and fabrication methodST MICROELECTRONICS SRL·Filed 1999·Granted Jul 31, 2001·26 cites·20 claims
- 0660US6573130B1Process for manufacturing electronic devices having non-salicidated non-volatile memory cells, non-salicidated HV transistors, and salicidated-junction LV transistorsST MICROELECTRONICS SRL·Filed 1999·Granted Jun 3, 2003·17 cites·11 claims
- 0755US6194270B1Process for the manufacturing of an electrically programmable non-volatile memory deviceST MICROELECTRONICS SRL·Filed 1998·Granted Feb 27, 2001·12 cites·15 claims
- 0852US6479347B1Simplified DSCP process for manufacturing FLOTOX EEPROM non-autoaligned semiconductor memory cellsST MICROELECTRONICS SRL·Filed 1999·Granted Nov 12, 2002·12 cites·15 claims
- 0949US5985718AProcess for fabricating memory cells with two levels of polysilicon for devices of EEPROM typeSGS THOMSON MICROELECTRONICS·Filed 1997·Granted Nov 16, 1999·12 cites·5 claims
- 1045US6320219B1Memory cell for EEPROM devices and corresponding fabricating processSGS THOMSON MICROELECTRONICS·Filed 2000·Granted Nov 20, 2001·2 cites·5 claims
- 1143US6576517B1Method for obtaining a multi-level ROM in an EEPROM process flowST MICROELECTRONICS SRL·Filed 1999·Granted Jun 10, 2003·8 cites·10 claims
- 1239US6177313B1Method for forming a muti-level ROM memory in a dual gate CMOS process, and corresponding ROM memory cellST MICROELECTRONICS SRL·Filed 1999·Granted Jan 23, 2001·4 cites·9 claims
- 1339US2002020872A1Memory cell of the EEPROM type having its threshold adjusted by implantationST MICROELECTRONICS SRL·Filed 2001·Application pending·0 cites
- 1437US6300181B1Process for manufacturing an electronic device including MOS transistors with salicided junctions and non-salicided resistorsST MICROELECTRONICS SRL·Filed 1999·Granted Oct 9, 2001·5 cites·15 claims
- 1534US6284607B1Method of making high-voltage HV transistors with drain extension in a CMOS process of the dual gate type with silicideST MICROELECTRONICS SRL·Filed 1999·Granted Sep 4, 2001·3 cites·13 claims
- 1633US6204531B1Non-volatile memory structure and corresponding manufacturing processST MICROELECTRONICS SRL·Filed 1999·Granted Mar 20, 2001·2 cites·13 claims
- 1733US6097057AMemory cell for EEPROM devices, and corresponding fabricating processSGS THOMSON MICROELECTRONICS·Filed 1997·Granted Aug 1, 2000·2 cites·13 claims
- 1831US6080626AMemory cell for EEPROM devices, and corresponding fabricating processSGS THOMSON MICROELECTRONICS·Filed 1997·Granted Jun 27, 2000·1 cites·6 claims
- 1930US6444526B1Simplified process for defining the tunnel area in non-aligned, non-volatile semiconductor memory cellsST MICROELECTRONICS SRL·Filed 1999·Granted Sep 3, 2002·0 cites·8 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →