Inventor · disambiguated record
Fazal Ur Rehman Qureshi
Also filed as: QURESHI FAZAL U R · QURESHI FAZAL UR REHMAN
9 granted patents·283 citations·filing 1995–1998
91Inventor score
Files withNAT SEMICONDUCTOR CORP9
Top patents by PatentIndex Score
9 records- 0183US5774475ATesting scheme that re-uses original stimulus for testing circuitry embedded within a larger circuitNAT SEMICONDUCTOR CORP·Filed 1996·Granted Jun 30, 1998·57 cites·18 claims
- 0281US5793778AMethod and apparatus for testing analog and digital circuitry within a larger circuitNAT SEMICONDUCTOR CORP·Filed 1997·Granted Aug 11, 1998·51 cites·34 claims
- 0378US5574731ASet/reset scan flip-flopsNAT SEMICONDUCTOR CORP·Filed 1995·Granted Nov 12, 1996·46 cites·8 claims
- 0466US5689466ABuilt in self test (BIST) for multiple RAMsNAT SEMICONDUCTOR CORP·Filed 1995·Granted Nov 18, 1997·53 cites·12 claims
- 0557US6182256B1Scan flip-flop that simultaneously holds logic values from a serial load and a subsequent parallel loadNAT SEMICONDUCTOR CORP·Filed 1998·Granted Jan 30, 2001·20 cites·15 claims
- 0653US6041426ABuilt in self test BIST for RAMS using a Johnson counter as a source of dataNAT SEMICONDUCTOR CORP·Filed 1997·Granted Mar 21, 2000·15 cites·1 claims
- 0750US5600658ABuilt-in self tests for large multiplier, adder, or subtractorNAT SEMICONDUCTOR CORP·Filed 1995·Granted Feb 4, 1997·17 cites·61 claims
- 0848US5774003AFlip-flop cell having clock skew protectionNAT SEMICONDUCTOR CORP·Filed 1996·Granted Jun 30, 1998·15 cites·17 claims
- 0940US6289480B1Circuitry for handling high impedance busses in a scan implementationNAT SEMICONDUCTOR CORP·Filed 1998·Granted Sep 11, 2001·9 cites·5 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →