Inventor · disambiguated record
Chester M. Nibby, Jr.
Also filed as: NIBBY CHESTER M JR · NIBBY JR CHESTER M
45 granted patents·1,891 citations·filing 1976–1997
99Inventor score
Files withHONEYWELL INF SYSTEMS30BULL HN INFORMATION SYST8NEC CORP2PACKARD BELL NEC2ZENITH DATA SYSTEMS CORP2
Top patents by PatentIndex Score
45 records- 0197US4303993AMemory present apparatusHONEYWELL INF SYSTEMS·Filed 1979·Granted Dec 1, 1981·110 cites·31 claims
- 0294US4317169AData processing system having centralized memory refreshHONEYWELL INF SYSTEMS·Filed 1979·Granted Feb 23, 1982·65 cites·11 claims
- 0393US4527251ARemap method and apparatus for a memory system which uses partially good memory devicesHONEYWELL INF SYSTEMS·Filed 1982·Granted Jul 2, 1985·112 cites·31 claims
- 0490US4468731AIdentification apparatus for use in a controller to facilitate the diagnosis of faultsHONEYWELL INF SYSTEMS·Filed 1981·Granted Aug 28, 1984·101 cites·41 claims
- 0589US5517648ASymmetric multiprocessing system with unified environment and distributed system functionsZENITH DATA SYSTEMS CORP·Filed 1995·Granted May 14, 1996·119 cites·3 claims
- 0689US4044330APower strobing to achieve a tri stateHONEYWELL INF SYSTEMS·Filed 1976·Granted Aug 23, 1977·34 cites·9 claims
- 0788US4366538AMemory controller with queue control apparatusHONEYWELL INF SYSTEMS·Filed 1980·Granted Dec 28, 1982·83 cites·26 claims
- 0888US4323965ASequential chip select decode apparatus and methodHONEYWELL INF SYSTEMS·Filed 1980·Granted Apr 6, 1982·88 cites·38 claims
- 0988US4060794AApparatus and method for generating timing signals for latched type memoriesHONEYWELL INF SYSTEMS·Filed 1976·Granted Nov 29, 1977·38 cites·9 claims
- 1087US4507730AMemory system with automatic memory configurationHONEYWELL INF SYSTEMS·Filed 1982·Granted Mar 26, 1985·80 cites·46 claims
- 1187US4185323ADynamic memory system which includes apparatus for performing refresh operations in parallel with normal memory operationsHONEYWELL INF SYSTEMS·Filed 1978·Granted Jan 22, 1980·32 cites·38 claims
- 1286US4369510ASoft error rewrite control systemHONEYWELL INF SYSTEMS·Filed 1980·Granted Jan 18, 1983·73 cites·40 claims
- 1383US4545010AMemory identification apparatus and methodHONEYWELL INF SYSTEMS·Filed 1983·Granted Oct 1, 1985·63 cites·49 claims
- 1482US4359771AMethod and apparatus for testing and verifying the operation of error control apparatus within a memoryHONEYWELL INF SYSTEMS·Filed 1980·Granted Nov 16, 1982·62 cites·40 claims
- 1581US5809340AAdaptively generating timing signals for access to various memory devices based on stored profilesPACKARD BELL NEC·Filed 1997·Granted Sep 15, 1998·99 cites·5 claims
- 1681US5345573AHigh speed burst read address generation with high speed transferBULL HN INFORMATION SYST·Filed 1991·Granted Sep 6, 1994·97 cites·10 claims
- 1780US4833601ACache resiliency in processing a variety of address faultsBULL HN INFORMATION SYST·Filed 1987·Granted May 23, 1989·65 cites·21 claims
- 1879US4523313APartial defective chip memory support systemHONEYWELL INF SYSTEMS·Filed 1982·Granted Jun 11, 1985·35 cites·30 claims
- 1979US4296467ARotating chip selection technique and apparatusHONEYWELL INF SYSTEMS·Filed 1978·Granted Oct 20, 1981·20 cites·33 claims
- 2076US4072853AApparatus and method for storing parity encoded data from a plurality of input/output sourcesHONEYWELL INF SYSTEMS·Filed 1976·Granted Feb 7, 1978·36 cites·27 claims
- 2175US4366539AMemory controller with burst mode capabilityHONEYWELL INF SYSTEMS·Filed 1980·Granted Dec 28, 1982·45 cites·36 claims
- 2272US4558429APause apparatus for a memory controller with interleaved queuing apparatusHONEYWELL INF SYSTEMS·Filed 1981·Granted Dec 10, 1985·39 cites·30 claims
- 2371US4370712AMemory controller with address independent burst mode capabilityHONEYWELL INF SYSTEMS·Filed 1980·Granted Jan 25, 1983·38 cites·38 claims
- 2469US4077565AError detection and correction locator circuitsHONEYWELL INF SYSTEMS·Filed 1976·Granted Mar 7, 1978·28 cites·21 claims
- 2565US4388684AApparatus for deferring error detection of multibyte parity encoded data received from a plurality of input/output data sourcesHONEYWELL INF SYSTEMS·Filed 1981·Granted Jun 14, 1983·30 cites·36 claims
- 2663US4432055ASequential word aligned addressing apparatusHONEYWELL INF SYSTEMS·Filed 1981·Granted Feb 14, 1984·28 cites·42 claims
- 2762US4361869AMultimode memory system using a multiword common bus for double word and single word transferHONEYWELL INF SYSTEMS·Filed 1980·Granted Nov 30, 1982·27 cites·31 claims
- 2862US4236203ASystem providing multiple fetch bus cycle operationHONEYWELL INF SYSTEMS·Filed 1978·Granted Nov 25, 1980·22 cites·19 claims
- 2959US4451880AMemory controller with interleaved queuing apparatusHONEYWELL INF SYSTEMS·Filed 1980·Granted May 29, 1984·24 cites·29 claims
- 3057US6311286B1Symmetric multiprocessing system with unified environment and distributed system functionsNEC CORP·Filed 1994·Granted Oct 30, 2001·20 cites·4 claims
- 3156US4910666AApparatus for loading and verifying a control store memory of a central subsystemBULL HN INFORMATION SYST·Filed 1986·Granted Mar 20, 1990·23 cites·5 claims
- 3255US5291580AHigh performance burst read data transfer operationBULL HN INFORMATION SYST·Filed 1991·Granted Mar 1, 1994·29 cites·12 claims
- 3350US5956522ASymmetric multiprocessing system with unified environment and distributed system functionsPACKARD BELL NEC·Filed 1995·Granted Sep 21, 1999·15 cites·1 claims
- 3449US4799222AAddress transform method and apparatus for transferring addressesHONEYWELL BULL·Filed 1987·Granted Jan 17, 1989·16 cites·20 claims
- 3546US4376972ASequential word aligned address apparatusHONEYWELL INF SYSTEMS·Filed 1980·Granted Mar 15, 1983·15 cites·41 claims
- 3645US4319324ADouble word fetch systemHONEYWELL INF SYSTEMS·Filed 1980·Granted Mar 9, 1982·14 cites·30 claims
- 3744US5491790APower-on sequencing apparatus for initializing and testing a system processing unitBULL HN INFORMATION SYST·Filed 1994·Granted Feb 13, 1996·16 cites·12 claims
- 3842US5341501AProcessor bus accessBULL HN INFORMATION SYST·Filed 1991·Granted Aug 23, 1994·13 cites·11 claims
- 3942US4190901APrinted circuit board apparatus which facilitates fabrication of units comprising a data processing systemHONEYWELL INF SYSTEMS·Filed 1977·Granted Feb 26, 1980·7 cites·17 claims
- 4040US5379378AData processing system having a bus command generated by one subsystem on behalf of another subsystemBULL HN INFORMATION SYST·Filed 1991·Granted Jan 3, 1995·13 cites·10 claims
- 4139US5522069ASymmetric multiprocessing system with unified environment and distributed system functionsZENITH DATA SYSTEMS CORP·Filed 1994·Granted May 28, 1996·7 cites·1 claims
- 4237US4255852AMethod of constructing a number of different memory systemsHONEYWELL INF SYSTEMS·Filed 1979·Granted Mar 17, 1981·5 cites·8 claims
- 4332US6125436ASymmetric multiprocessing system with unified environment and distributed system functions wherein bus operations related storage spaces are mapped into a single system address spaceNEC CORP·Filed 1997·Granted Sep 26, 2000·3 cites·8 claims
- 4432US4302735ADelay line compensation networkHONEYWELL INF SYSTEMS·Filed 1979·Granted Nov 24, 1981·1 cites·20 claims
- 4530US4916601AMeans for transferring firmware signals between a control store and a microprocessor means through a reduced number of connections by transfer according to firmware signal functionBULL HN INFORMATION SYST·Filed 1988·Granted Apr 10, 1990·1 cites·4 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →