Inventor · disambiguated record
Javier Carretero Casado
Also filed as: CASADO JAVIER C · CASADO JAVIER CARRETERO
15 granted patents·2 pending applications·58 citations·filing 2007–2013
91Inventor score
Top patents by PatentIndex Score
17 records- 0189US8291168B2Disabling cache portions during low voltage operationsWILKERSON CHRISTOPHER·Filed 2011·Granted Oct 16, 2012·12 cites·20 claims
- 0284US9071281B2Selective provision of error correction for memoryINTEL CORP·Filed 2013·Granted Jun 30, 2015·10 cites·23 claims
- 0381US8103830B2Disabling cache portions during low voltage operationsWILKERSON CHRISTOPHER·Filed 2008·Granted Jan 24, 2012·9 cites·20 claims
- 0474US9678878B2Disabling cache portions during low voltage operationsWILKERSON CHRISTOPHER·Filed 2012·Granted Jun 13, 2017·3 cites·5 claims
- 0571US9075904B2Vulnerability estimation for cache memoryINTEL CORP·Filed 2013·Granted Jul 7, 2015·3 cites·22 claims
- 0671US7747913B2Correcting intermittent errors in data storage structuresINTEL CORP·Filed 2007·Granted Jun 29, 2010·5 cites·10 claims
- 0770US9170947B2Recovering from data errors using implicit redundancyVERA XAVIER·Filed 2011·Granted Oct 27, 2015·3 cites·23 claims
- 0868US9405647B2Register error protection through binary translationVERA XAVIER·Filed 2011·Granted Aug 2, 2016·2 cites·19 claims
- 0968US8069376B2On-line testing for decode logicMONFERRER PEDRO CHAPARRO·Filed 2009·Granted Nov 29, 2011·4 cites·20 claims
- 1068US7577015B2Memory content inverting to minimize NTBI effectsINTEL CORP·Filed 2007·Granted Aug 18, 2009·4 cites·9 claims
- 1161US8352812B2Protecting data storage structures from intermittent errorsINTEL CORP·Filed 2007·Granted Jan 8, 2013·2 cites·5 claims
- 1260US9608922B2Traffic control on an on-chip networkMONCHIERO MATTEO·Filed 2011·Granted Mar 28, 2017·1 cites·11 claims
- 1348US8477558B2Memory apparatuses with low supply voltagesABELLA JAUME·Filed 2008·Granted Jul 2, 2013·0 cites·22 claims
- 1445US2009150653A1Mechanism for soft error detection and recovery in issue queuesMONFERRER PEDRO CHAPARRO·Filed 2007·Application pending·0 cites
- 1544US9619309B2Enforcing different operational configurations for different tasks for failure rate based control of processorsINTEL CORP·Filed 2012·Granted Apr 11, 2017·0 cites·23 claims
- 1637US2014237018A1Tracking distributed execution on on-chip multinode networks without a centralized mechanismMONCHIERO MATTEO·Filed 2011·Application pending·0 cites
- 1735US10020037B2Capacity register fileABELLA JAUME·Filed 2007·Granted Jul 10, 2018·0 cites·15 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →