Inventor · disambiguated record
Frank Scott Johnson
Also filed as: JOHNSON FRANK · JOHNSON FRANK S · JOHNSON FRANK SCOTT
44 granted patents·7 pending applications·478 citations·filing 1977–2019
98Inventor score
Files withTEXAS INSTRUMENTS INC20GLOBALFOUNDRIES INC11JOHNSON FRANK SCOTT3ADVANCED MICRO DEVICES INC2JOHNSON FRANK2
Top patents by PatentIndex Score
51 records- 0196US7960287B2Methods for fabricating FinFET structures having different channel lengthsGLOBALFOUNDRIES INC·Filed 2010·Granted Jun 14, 2011·25 cites·9 claims
- 0295US7687339B1Methods for fabricating FinFET structures having different channel lengthsADVANCED MICRO DEVICES INC·Filed 2009·Granted Mar 30, 2010·38 cites·18 claims
- 0394US8039326B2Methods for fabricating bulk FinFET devices having deep trench isolationGLOBALFOUNDRIES INC·Filed 2009·Granted Oct 18, 2011·31 cites·19 claims
- 0493US8603893B1Methods for fabricating FinFET integrated circuits on bulk semiconductor substratesWEI ANDY C·Filed 2012·Granted Dec 10, 2013·56 cites·15 claims
- 0592US8383503B2Methods for forming semiconductor structures using selectively-formed sidewall spacersGLOBALFOUNDRIES INC·Filed 2009·Granted Feb 26, 2013·16 cites·19 claims
- 0689US8912603B2Semiconductor device with stressed fin sectionsLUNING SCOTT·Filed 2011·Granted Dec 16, 2014·11 cites·20 claims
- 0788US8404592B2Methods for fabricating FinFET semiconductor devices using L-shaped spacersLUNING SCOTT·Filed 2009·Granted Mar 26, 2013·14 cites·14 claims
- 0888US7829466B2Methods for fabricating FinFET structures having different channel lengthsGLOBALFOUNDRIES INC·Filed 2009·Granted Nov 9, 2010·13 cites·9 claims
- 0987US8729609B2Integrated circuits including multi-gate transistors locally interconnected by continuous fin structure and methods for the fabrication thereofJOHNSON FRANK SCOTT·Filed 2010·Granted May 20, 2014·10 cites·10 claims
- 1085US8039349B2Methods for fabricating non-planar semiconductor devices having stress memoryGLOBALFOUNDRIES INC·Filed 2009·Granted Oct 18, 2011·9 cites·4 claims
- 1185US7977174B2FinFET structures with stress-inducing source/drain-forming spacers and methods for fabricating the sameGLOBALFOUNDRIES INC·Filed 2009·Granted Jul 12, 2011·11 cites·20 claims
- 1285US7930656B2System and method for making photomasksTEXAS INSTRUMENTS INC·Filed 2007·Granted Apr 19, 2011·8 cites·11 claims
- 1384US8268727B2Methods for fabricating FinFET semiconductor devices using planarized spacersJOHNSON FRANK S·Filed 2009·Granted Sep 18, 2012·13 cites·20 claims
- 1481US8030144B2Semiconductor device with stressed fin sections, and related fabrication methodsGLOBALFOUNDRIES INC·Filed 2009·Granted Oct 4, 2011·7 cites·17 claims
- 1581US7985639B2Method for fabricating a semiconductor device having a semiconductive resistor structureGLOBALFOUNDRIES INC·Filed 2009·Granted Jul 26, 2011·8 cites·20 claims
- 1677US9000534B2Method for forming and integrating metal gate transistors having self-aligned contacts and related structureKNORR ANDREAS H·Filed 2009·Granted Apr 7, 2015·9 cites·19 claims
- 1776US8865596B2Methods for forming semiconductor structures using selectively-formed sidewall spacersJOHNSON FRANK SCOTT·Filed 2013·Granted Oct 21, 2014·3 cites·7 claims
- 1875US9257325B2Semiconductor structures and methods for forming isolation between Fin structures of FinFET devicesKNORR ANDREAS·Filed 2009·Granted Feb 9, 2016·8 cites·13 claims
- 1974US8192641B2Methods for fabricating non-planar electronic devices having sidewall spacers formed adjacent selected surfacesJOHNSON FRANK SCOTT·Filed 2009·Granted Jun 5, 2012·4 cites·20 claims
- 2074US7910422B2Reducing gate CD bias in CMOS processingTEXAS INSTRUMENTS INC·Filed 2008·Granted Mar 22, 2011·5 cites·26 claims
- 2173US7763540B2Method of forming a silicided gate utilizing a CMP stackTEXAS INSTRUMENTS INC·Filed 2007·Granted Jul 27, 2010·5 cites·13 claims
- 2273US6518111B1Method for manufacturing and structure of semiconductor device with dielectric diffusion source and CMOS integrationTEXAS INSTRUMENTS INC·Filed 2001·Granted Feb 11, 2003·15 cites·2 claims
- 2373US4201428ACabinet assemblyMARVEL METAL PRODUCTS·Filed 1978·Granted May 6, 1980·34 cites·11 claims
- 2472US8558318B2Integration scheme for changing crystal orientation in hybrid orientation technology (HOT) using direct silicon bonded (DSB) substratesPINTO ANGELO·Filed 2011·Granted Oct 15, 2013·2 cites·6 claims
- 2571US8736061B2Integrated circuits having a continuous active area and methods for fabricating sameJOHNSON FRANK·Filed 2012·Granted May 27, 2014·3 cites·20 claims
- 2670US7892908B2Integration scheme for changing crystal orientation in hybrid orientation technology (HOT) using direct silicon bonded (DSB) substratesTEXAS INSTRUMENTS INC·Filed 2008·Granted Feb 22, 2011·2 cites·14 claims
- 2769US6030864AVertical NPN transistor for 0.35 micrometer node CMOS logic technologyTEXAS INSTRUMENTS INC·Filed 1997·Granted Feb 29, 2000·30 cites·8 claims
- 2865US4090755ACabinet assemblyMARVEL METAL PRODUCTS COMPANY·Filed 1977·Granted May 23, 1978·27 cites·2 claims
- 2960US6570242B1Bipolar transistor with high breakdown voltage collectorTEXAS INSTRUMENTS INC·Filed 1998·Granted May 27, 2003·16 cites·6 claims
- 3057US7892906B2Method for forming CMOS transistors having FUSI gate electrodes and targeted work functionsTEXAS INSTRUMENTS INC·Filed 2008·Granted Feb 22, 2011·1 cites·24 claims
- 3156US9123570B2Integration scheme for changing crystal orientation in hybrid orientation technology (HOT) using direct silicon bonded (DSB) substratesTEXAS INSTRUMENTS INC·Filed 2013·Granted Sep 1, 2015·0 cites·6 claims
- 3256US7943451B2Integration scheme for reducing border region morphology in hybrid orientation technology (HOT) using direct silicon bonded (DSB) substratesTEXAS INSTRUMENTS INC·Filed 2008·Granted May 17, 2011·0 cites·15 claims
- 3354US7456070B2Method of fabricating a bipolar transistor with high breakdown voltage collectorTEXAS INSTRUMENTS INC·Filed 2002·Granted Nov 25, 2008·5 cites·8 claims
- 3453US6130136ABipolar transistor with L-shaped base-emitter spacerTEXAS INSTRUMENTS INC·Filed 1998·Granted Oct 10, 2000·15 cites·16 claims
- 3549US2010308382A1Semiconductor structures and methods for reducing silicon oxide undercuts in a semiconductor substrateGLOBALFOUNDRIES INC·Filed 2009·Application pending·0 cites
- 3649US2010267237A1Methods for fabricating finfet semiconductor devices using ashable sacrificial mandrelsADVANCED MICRO DEVICES INC·Filed 2009·Application pending·0 cites
- 3749US2010308409A1Finfet structures with fins having stress-inducing caps and methods for fabricating the sameGLOBALFOUNDRIES INC·Filed 2009·Application pending·0 cites
- 3848US2011180881A1Integration scheme for reducing border region morphology in hybrid orientation technology (hot) using direct silicon bonded (dsb) substratesTEXAS INSTRUMENTS INC·Filed 2011·Application pending·0 cites
- 3946US11195947B2Semiconductor device with doped region adjacent isolation structure in extension regionGLOBALFOUNDRIES US INC·Filed 2019·Granted Dec 7, 2021·0 cites·19 claims
- 4046US7785970B2Method of forming source and drain regions utilizing dual capping layers and split thermal processesTEXAS INSTRUMENTS INC·Filed 2007·Granted Aug 31, 2010·0 cites·28 claims
- 4145US7960280B2Process method to fully salicide (FUSI) both N-poly and P-poly on a CMOS flowTEXAS INSTRUMENTS INC·Filed 2007·Granted Jun 14, 2011·0 cites·21 claims
- 4245US2010308440A1Semiconductor structures and methods for stabilizing silicon-comprising structures on a silicon oxide layer of a semiconductor substrateGLOBALFOUNDRIES INC·Filed 2009·Application pending·0 cites
- 4345US2008233747A1Semiconductor Device Manufactured Using an Improved Plasma Etch Process for a Fully Silicided Gate Flow ProcessTEXAS INSTRUMENTS INC·Filed 2007·Application pending·0 cites
- 4444US8138045B2Method of forming sidewall spacers to reduce formation of recesses in the substrate and increase dopant retention in a semiconductor deviceNANDAKUMAR MAHALINGAM·Filed 2008·Granted Mar 20, 2012·0 cites·8 claims
- 4541US6797577B2One mask PNP (or NPN) transistor allowing high performanceTEXAS INSTRUMENTS INC·Filed 2002·Granted Sep 28, 2004·3 cites·25 claims
- 4641US4208098AOdor dispensing system for hand-held stereoscopic viewer and replaceable container thereforJOHNSON FRANK·Filed 1978·Granted Jun 17, 1980·9 cites·3 claims
- 4741US2008206973A1Process method to optimize fully silicided gate (FUSI) thru PAI implantTEXAS INSTRUMENTS INC·Filed 2007·Application pending·0 cites
- 4839US6130122AMethod for forming a BiCMOS integrated circuit with Nwell compensation implant and methodTEXAS INSTRUMENTS INC·Filed 1998·Granted Oct 10, 2000·5 cites·12 claims
- 4937US9336345B2Methods for converting planar designs to FinFET designs in the design and fabrication of integrated circuitsGLOBALFOUNDRIES SG PTE LTD·Filed 2013·Granted May 10, 2016·0 cites·19 claims
- 5035US4601187ATwisting apparatus and methodWELLFORM ENG·Filed 1984·Granted Jul 22, 1986·7 cites·12 claims
Showing the top 50 of 51 patent records by PatentIndex Score.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →